• International journal of advanced smart convergence
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• v.11 no.1
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• pp.28-35
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• 2022

This paper presents a performance evaluation of real-time Linux for industrial real-time platforms. On industrial platforms, multicore processors are popular due to their work distribution efficiency and cost-effectiveness. Multicore processors, however, are not designed for applications with real-time constraints, and their performance capabilities depend on their core configurations. In order to assess the feasibility of a multicore processor for real-time applications, we conduct a performance evaluation of a general processor and a low-power processor to provide an experimental environment of real-time Linux on both Xenomai and RT-preempt considering the multicore configuration. The real-time performance is evaluated through scheduling latency and in an environment with loads on the CPU, memory, and network to consider an actual situation. The results show a difference between a low-power and a general-purpose processor, but from developer's point of view, it shows that the low-power processor is a proper solution to accommodate low power situations.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1986.04a
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• pp.181-183
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• 1986

This paper describes the design and implementation of post processor for Numerical control programing which prepare control paper tape of NC machine. The post processor that we developed reflects modular program design methodology to improve flexibility about variety NC machine. Also, the designed post processor is able to link with general NC system as APT(Automatically programing tools) system or general CAD/CAM system.

• 한국전산유체공학회:학술대회논문집
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• 2004.10a
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• pp.53-59
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• 2004

A general purpose program NUFLEX for the analysis of 3-D heat/fluid flow in complex geometry with pre/post processor have been developed, which consists of a flow solver based on FVM and a dedicated pre/post processor. The program employs a general non-orthogonal grid system and solve laminar and turbulent (lows with standard and RNG $\kappa-\epsilon$ turbulence models. NUFLEX is capable of analysing two-phase flow with topologically complex interface, turbulent diffusion combustion, solidification problems and magnetic flow. For the purpose of verification of the program and testing the applicability, several practical problems are solved and compared with the available data. Comparison of the NUFLEX results with that by the STAR-CD program has been also made for the same flow configuration and grid structure.

• Journal of IKEEE
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• v.13 no.2
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• pp.253-259
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• 2009

In this paper, we propose a novel architecture of a general graphics shader processor without a dedicated hardware. Recently, mobile devices require the high performance graphics processor as well as the small size, low power. The proposed shader processor is a GP-GPU(General-Purpose computing on Graphics Processing Units) to execute the whole OpenGL ES 2.0 graphics pipeline by using shader instructions. It does not require the separate dedicate H/W such as rasterization on this fully programmable capability. The fully programmable 3D graphics shader processor can reduce much of the graphics hardware. The chip size of the designed shader processor is reduced 60% less than the sizes of previous processors.

• Proceedings of the KIEE Conference
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• 1990.11a
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• pp.439-442
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• 1990

A powerful general purpose image processing processor is developed using a high-speed DSP chip, TMS320C30. The image processing processor, compatible to the standard VME bus, is composed of VME bus interface unit, video rate image grabbing/coding unit, TMS320C30 interface unit and bank of high-speed SRAMs. The performance is evaluated experimentally with the general image processing algorithms and the results show that the developed processor is capable of high speed image processing.

• Journal of computational fluids engineering
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• v.12 no.2
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• pp.8-13
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• 2007

A general purpose program NUFLEX for the analysis 3-D thermo/fluid flow and pre/post processor in complex geometry has been developed, which consists of a flow solver based on FVM and GUI based pre/post processor. The solver employs a general non-orthogonal grid system with structured grid and solves laminar and turbulent flows with standard/RNG $k-{\varepsilon}$ turbulence model. In addition, NUFLEX is incorporated with various physical models, such as interfacial tracking, cavitation, MHD, melting/solidification and spray models. For the purpose of evaluation of the program and testing the applicability, many actual problems are solved and compared with the available data. Comparison of the results with that by STAR-CD or FLUENT program has been also made for the same flow configuration and grid structure to test the validity of NUFLEX.

• 한국전산유체공학회:학술대회논문집
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• 2007.04a
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• pp.87-90
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• 2007

A general purpose program NUFLEX for the analysis 3-D thermo/fluid flow and pre/post processor in complex geometry has been developed, which consists of a flow solver based on FVM and GUI based pre/post processor. The solver employs a general non-orthogonal grid system with structured grid and solves laminar and turbulent flows with standard/RNG ${\kappa}-{\varepsilon}\;SST$ turbulence model. In addition, NUFLEX is incorporated with various physical models, such as interfacial tracking, cavitation, MHD, melting/solidification and spray model. For the purpose of verification of the program and testing the applicability, many actual problems are solved and compared with the available data. Comparison of the results with that by STAR-CD or FLUENT program has been also made for the same flow configuration and grid structure to test the validity of NUFLEX.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.2 s.344
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• pp.51-59
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• 2006

Von Neumann architecture suffers from the interface between the central processing unit and the memory, which is called 'Von Neumann bottleneck' In this paper, we propose a scalable general-purpose associative processor (AP) based on content-addressable memory (CAM) which solves this problem and is suitable for the search-oriented applications. We propose an efficient instruction set and a structural scalability to extend for larger applications. We define twelve instructions and provide some reduced instructions to speed up which execute two instructions in a single instruction cycle. The proposed AP performs in a bit-serial, word-parallel fashion and can be considered as a 32-bit general-purpose parallel processor with a massively parallel SIMD structure. We design and simulate a maximum/minumum search greater-than/less-than search, and parallel addition to verify the proposed architecture. The algorithms are executed in a constant time O(k) regardless of the number of input data.

• Journal of Electrical Engineering and information Science
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• v.2 no.3
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• pp.105-112
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• 1997

The performance of a shared memory multiprocessor system is very sensitive to process scheduling. w can enhance the performance of a whole system as well as of an individual process by taking the multiprocessor characteristics into account in the design of the process scheduler. In this paper, we proposed a general purpose scheduler for a shared memory multiprocessor, called the Two-Level Multi-Scan (TLMS) process scheduler, that considers the processor affinity loosely and decreases the interference among multiple processors greatly. The TLMS scheduler is composed of a local scheduler at each processor and a semi-global scheduler that balances the load among processors. In particular, the semi-global scheduler tries to minimize priority inversion, which is an important factor of the system performance. The TLMS scheduler also tries to reduce the number of resources to be shared and improves the processor utilization. to meet these requirements, th semi-global scheduler interacts with the operation of the local scheduler when a need arises, thus the name is loose processor-affinity. We also show that the proposed scheduling technique can be extended for other types of resources making it a general purpose resource management queue.

• The Journal of Information Technology
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• v.10 no.3
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• pp.33-45
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• 2007

Systolic Array Processor is used for designing the special purpose processor in Digital Signal Processing, Computer Graphics, Neural Network Applications etc., since it has the characteristic of parallelism, pipeline processing and architecture of regularity. But, in case of using general design method, it has intial waiting period as large as No. of PE-1. And if the connected system needs parallel and simultaneous outputs, processor has some problems of the performance, since it generates only one output at each clock in output state. So in this paper, one dimensional Systolic Array Processor that is designed according to the dependance of data and operations using the partitioned sub-matrix is proposed for the purpose of improving the performance. 1-D Systolic Array using 4 partitioned sub-matrix has efficient method in case of considering those two problems.