• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.2A
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• pp.129-136
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• 2005

A multiplier generator, VPM_Gen (Variable-Precision Multiplier Generator), which generates Verilog-HDL models of multiplier cores with user-defined bit-width specification, is described. The bit-widths of operands are parameterized in the range of $8-bit{\sim}32-bit$ with 1-bit step, and the product from multiplier core can be truncated in the range of $8-bit{\sim}64-bit$ with 2-bit step, resulting that the VPM_Gen can generate 3,455 multiplier cores. In the case of truncating multiplier output, by eliminating the circuits corresponding to the truncation part, the gate counts and power dissipation can be reduced by about 40% and 30%, respectively, compared with full-precision multiplier. As a result, an area-efficient and low-power multiplier core can be obtained. To minimize truncation error, an adaptive error-compensation method considering the number of truncation bits is employed. The multiplier cores generated by VPM_Gen have been verified using Xilinx FFGA board and logic analyzer.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.659-662
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• 2005

A parameterized FFT/IFFT core generator (PFFT_CoreGen) is designed, which can be used as an essential IP (Intellectual Property) in various OFDM modem designs. The PFFT_CoreGen generates Verilog-HDL models of FFT cores in the range of 64 ${\sim}$ 2048-point. To optimize the performance of the generated FFT cores, the PFFT_CoreGen can select the word-length of input data, internal data and twiddle factors in the range of 8-b ${\sim}$ 24-b. Some design techniques for low-power design are considered from algorithm level to circuit level.

• Aerospace Engineering and Technology
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• v.12 no.1
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• pp.120-127
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• 2013

Recently, In Aerospace area the interest of open source software is increasing. One of examples is celestia that is used for visualizing space environment with 3D. Celestia that is open source software has many advantages. First is very easy to use, second is that it can extend new features easily with script language. It is very useful to extend with other systems. But, celestia has a few of remote control features from remote site. In this paper I describe design and implementation of remote control module using UDP communication protocol between celestia and GenSim that is satellite simulation software developed by KARI and describe the problem and solution items are found during development duration.

• Journal of Astronomy and Space Sciences
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• v.28 no.3
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• pp.241-252
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• 2011

A simulated network protocol provides the capability of distributed simulation to a generic simulator. Through this, full coverage of management of data and service handling among separated simulators is achieved. The distributed simulation environment is much more conducive to handling simulation load balancing and hazard treatment than a standalone computer. According to the simulated network protocol, one simulator takes on the role of server and the other simulators take on the role of client, and client is controlled by server. The purpose of the simulated network protocol is to seamlessly connect multiple simulator instances into a single simulation environment. This paper presents the development of a simulated network (simNetwork) that provides the capability of distributed simulation to a generic simulator (GenSim), which is a software simulator of satellites that has been developed by the Korea Aerospace Research Institute since 2010, to use as a flight software validation bench for future satellite development.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.3A
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• pp.368-376
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• 2006

This paper describes a Fcore_GenSim(Parameterized FFT Core Generation & Simulation Program), which can be used as an essential If(Intellectual Property) in various OFDM modem designs. The Fcore_Gensim is composed of two parts, a parameterized core generator(PFFT_CoreGen) that generates Verilog-HDL models of FFT cores, and a fixed-point FFT simulator(FXP_FFTSim) which can be used to estimate the SQNR performance of the generated cores. The parameters that can be specified for core generation are FFT length in the range of 64 ~2048-point and word-lengths of input/output/internal/twiddle data in the range of 8-b "24-b with 2-b step. Total 43,659 FFT cores can be generated by Fcore_Gensim. In addition, CBFP(Convergent Block Floating Point) scaling can be optionally specified. To achieve an optimized hardware and SQNR performance of the generated core, a hybrid structure of R2SDF and R2SDC stages and a hybrid algorithm of radix-2, radix-2/4, radix-2/4/8 are adopted according to FFT length and CBFP scaling.

• The Transactions of the Korea Information Processing Society
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• v.3 no.7
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• pp.1773-1780
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• 1996

KBANN (knowledge-based artificial neural network) combining the symbolic approach and the numerical approach has been shown to be more effective than other machine learning models. However KBANN doesn't have the theory refinement ability because the topology of network can't be altered dynamically. Although TopGen was proposed to extend the ability of KABNN in this respect, it also had some defects due to the link-ing of hidden nodes to input nodes and the use of beam search. The algorithm which could solve this TopGen's defects, by adding the hidden nodes linked to next layer nodes and using hill-climbing search with backtracking, is designed.

• Proceedings of the Zoological Society Korea Conference
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• 1998.10b
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• pp.80-80
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• 1998

No Abstract, See Full Text

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.2A
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• pp.177-183
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• 2009

In this paper, we propose an improved anti-collision algorithm. We have designed an anti-collision unit using this algorithm for the 18000-6 Type C Class 1 Generation 2 standard (Gen2). The Gen2 standard uses a Q-algorithm for incremental method on the Dynamic Slot-Aloha algorithm. It has basically enhanced performance over the Slot-Aloha algorithm. Unfortunately, there are several non-clarified parts: initial $Q_{fp}$ value, weighted C, and the ending point of the algorithm. If an incorrect value is selected, it causes degradation in performance. Thus we propose an improved anti-collision algorithm by clearly defining the vague parts of the existing algorithm. Simulation results showed an improved performance of up to 34.8% using an optimized value of C and the initial $Q_{fp}$ value. With the ending condition, performance is 34.7%. The anti-collision unit is designed using the Verilog HDL. The module was synthesized using Synopsys' Design Compiler and the TSMC $0.2{\mu}m$ standard cell library. The synthesized result yielded 3,847 gates, and was guaranteed under the proposed working frequency of 19.2MHz.

• Defense and Technology
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• no.5 s.243
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• pp.54-61
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• 1999

미 육군은 다수의 새로운 체계와 기존 차량의 성능 개선을 위해 타이타늄을 평가하고 있다. UDLP(United Defence Limited Pantnership)에 의해 개발된 AGS(The Armored Gen System)는 타이타늄 부가장갑을 사용하고 있다. 아마도 최대의 성능개선 계획은 방호력이 증대된 확장형 M113 인원 수송 차량(APC, 전 세계에 60,000대 이상 배치 운영 중)일 것이다. 측면 방호력 증대를 위해 1.25인치 두께의 부가 장갑판과 전면장갑으로 2인치 두께 판이 고려되고 있다

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.1A
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• pp.83-90
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• 2007

In this paper, we propose an implementation and an algorithm of 'Jitter and Glitch Removing Circuit' for UHF RFID reader system based on ISO/IEC 18000-6C standard. We analyze the response of TI(Texas Instrument) Gen2 tag with a reader using the proposed algorithm. In ISO/IEC 18000-6C standard, a bit rate accuracy(tolerance) is up to +/-22% during tag-to-interrogator communication and +/-1% during interrogator-to-tag communication. In order to solve tolerance problems, we implement the Jitter and Glitch Removing Circuit using the concept of tolerance and tolerance-accumulation instead of PLL(DPLL, ADPLL). The main clock is 19.2MHz and the LF(Link Frequency) is determined as 40kHz to meet the local radio regulation in korea. As a result of simulations, the error-rate is zero within 15% tolerance of tag responses. And in the case of using the adaptive LF generation circuit, the error-rate varies from 0.000589 to zero between 15% and 22% tolerance of tag responses. In conclusion, the error-rate is zero between 0%-22% tolerance of tag response specified in ISO/IEC 18000-6C standard.