• Journal of the Institute of Electronics Engineers of Korea SD
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• 제44권9호
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• pp.1-9
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• 2007

For an efficient implementation of cryptosystems based on arithmetic in a finite field $GF(2^n)$, their hardware implementation is an important research topic. To construct a multiplier with low area complexity, the divide-and-conquer technique such as the original Karatsuba-Ofman method and multi-segment Karatsuba methods is a useful method. Leone proposed an efficient parallel multiplier with low area complexity, and Ernst at al. proposed a multiplier of a multi-segment Karatsuba method. In [1], the authors proposed new $MSK_5$ and $MSK_7$ methods with low area complexity to improve Ernst's method. In [3], the authors proposed a method which combines $MSK_2$ and $MSK_3$. In this paper we propose an efficient multiplication method by combining $MSK_2,\;MSK_3\;and\;MSK_5$ together. The proposed method reduces $116{\cdot}3^l$ gates and $2T_X$ time delay compared with Gather's method at the degree $25{\cdot}2^l-2^l with l>0.

• Journal of Navigation and Port Research
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• 제26권1호
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• pp.106-111
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• 2002

The estimation of pile bearing capacity is important since the design details are determined from the result. There are numerous ways of determining the pile design load, but only few of them are chosen in the actual design. According to the recent investigation in Korea, the formulas proposed by Meyerhof based on the SPT N values are most frequently chosen in the design stage. In the study, various static and dynamic formulas have been used in predicting the allowable bearing capacity of a pile. Further, the reliability of these formulas has been verified by comparing the perdicted values with the static and dynamic load test measurements. Also, in most cases, these methods of pile bearing capacity determination do not take the time effect consideration, the actual allowable load as determined from pile load test indicates severe deviation from the design value. The principle results of this study are summarized as follows : As a result of estimate the reliability in criterion of the Davisson method, t was showed that Terzaghi & Peck >Chin>Meyerhof > Modified Meyerhof method was the most reliable method for the prediction of bearing capacity. Comparisons of the various pile-driving formulas showed that Modified Engineering News was the most reliable method. However, a significant error happened between dynamic bearing capacity equation was judged that uncertainty of hammer efficiency, characteristics of variable, time effect etc... was not considered. As a result of considering time effect increased skin friction capacity higher than end bearing capacity. It was found out that it would be possible to increase the skin friction capacity 1.99 times higher than a driving. As a result of considering 7 day's time effect, it was obtained that Engineering news, Modified Engineering News, Hiley, Danish, Gates, CAPWAP(CAse Pile Wave Analysis Program) analysis for relation, repectively, $Q_{u(Restrike)} / Q_{u(EOID)} = 0.98t_{0.1}$ , $0.98t_{0.1}$, $1.17t_{0.1}$, $0.88t_{0.1}$, $0.89t_{0.1}$, $0.97t_{0.1}$.

• Journal of the Korean Institute of Telematics and Electronics C
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• 제36C권8호
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• pp.1-9
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• 1999

Timing-level circuit analyses are used to obtain fast and accurate results, and the analysis of gate and interconnect delay is necessary to validate the correctness of circuit design. This paper proposes an efficient algorithm which simultaneously calculates the gate delay and the transition time of linearized voltage source for subsequent interconnect delay calculation. The notion of effective capacitance is used to calculate the gate delay and the transition time of linearized voltage source which considers the on-resistance of driving gate. The procedure for obtaining the gate delay and the transition time of linearized voltage source has been developed through an iterative operation using the precharacterized data of gates. While previous methods require extra information for the transition time calculation of linearized voltage sources, our method uses the derived data during the gate delay calculation process, which does not require any change in the precharacterization process.

• Journal of the Institute of Electronics Engineers of Korea SD
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• 제48권11호
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• pp.18-26
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• 2011

This paper describes a multi-mode LDPC decoder which supports three block lengths(648, 1296, 1944) and four code rates(1/2, 2/3, 3/4, 5/6) of IEEE 802.11n wireless LAN standard. To minimize hardware complexity, it adopts a block-serial (partially parallel) architecture based on the layered decoding scheme. A novel memory reduction technique devised using the min-sum decoding algorithm reduces the size of check-node memory by 47% as compared to conventional method. From fixed-point modeling and Matlab simulations for various bit-widths, decoding performance and optimal hardware parameters such as fixed-point bit-width are analyzed. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a 0.18-${\mu}m$ CMOS cell library. It has 219,100 gates and 45,036 bits RAM, and the estimated throughput is about 164~212 Mbps at 50 MHz@2.5v.

• Journal of KIISE:Computer Systems and Theory
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• 제27권7호
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• pp.684-694
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• 2000

For designing circuits for low power systems, the capacitance is an important factor for the power dissipation. Since the capacitance of a gate is proportional to the area of the gate, we can reduce the total power consumption of a circuit by reducing the total area of gates, where total area is a simple sum of all gate areas in the circuit. To reduce the total area, transistor resizing can be used. While resizing transistors, inserting buffer in the proper position can help reduce the total area. In this paper we propose two methods for concurrent transistor sizing and buffer insertion. One method uses template window simulation and the other uses extrapolation. Experimental results show that concurrent transistor sizing with buffer insertion achieved 10-20% more reduction of the total area than when it was done without buffer insertion and template window simulation is more efficient than extrapolation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• 제42권4호
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• pp.37-44
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• 2005

In this paper, a new type of the TC-to-BC encoder for high speed flash ADC's, called the Successive Selection Encoder (SSE), is proposed. In contrast to the conventional fat tree encoder based on OR operations, the W- outputs, in the new design, are obtained directly from TC inputs through simple MUX operations. The detailed structure of the SSE has been determined systematically by the method of the logical effort and the simulation oil Hynix 0.25um process. The theoretical and experimental results show that (1) it is not required to generate one-out-of-n signals, (2) the number of gates is reduced by the factor of 1/3, and (3) the speed is improved more than 2-times, compared to the fat tree encoder. It is speculated that the SSE proposed in this study is an effective solution for bottleneck problems in high speed ADCs.

• Journal of the Institute of Electronics Engineers of Korea CI
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• 제45권2호
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• pp.41-47
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• 2008

Most of media compression CODECs adopts the variable length coding method. This paper proposes special registers and instruction set for bit stream process in order to accelerate the decoding process of the variable length code. The instruction set shares the conventional data path to minimize additional costs. And bit stream is read from the memory instead of the special port. Therefore the instruction set minimizes the change of the processor, and is adopted without any additional input controller and buffer, and accelerate decoding process of variable length code. The data path of the instruction set needs additional 65 bits memory and 344 equivalent gates, 0.19 ns delay under TSMC $0.25{\mu}m$ technology. The instruction set reduced the execution time of the variable length code decoding process in H.264/AVC by about 55%.

• The Journal of Korean Institute of Communications and Information Sciences
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• 제24권7B호
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• pp.1393-1399
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• 1999

In this paper, a VLSI design of the convolutional codec chip of code rate r=l/3, and constraint length K=9 is presented, which is able to correct errors of the received data when transmitted data is corrupted in channels. The circuit design mainly aimed for simple implementation. In the decoder, Viterbi algorithm with 3-bit soft-decision is employed. For information sequence updating and storage, the register exchange method is employed, where the register length is 5$\times$K(45 stages). The codec chip is designed using VHDL language and Design Analyzer and VHDL Simulator of Synopsys are used for simulation and synthesis. The chip is composed of ENCODER block, ALIGN block, BMC block, ACS block, SEL_MIN block and REG_EXCH block. The operation of the codec chip is verified though the logic simulations, where several error conditions are assumed. As a result of the timing simulation after synthesis, the decoding speed of 325.5Kbps is achieved, and 6,894 gates is used.

• Journal of the Korea Institute of Information and Communication Engineering
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• 제20권1호
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• pp.123-130
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• 2016

In this paper, a high-performance arithmetic unit which can efficiently accelerate a number of algorithms for multimedia application was designed. The 3-stage pipelined arithmetic unit can execute 38 operations for complex and fixed-point data by using efficient configuration for four 16-bit by 16-bit multipliers, new sign extension method for carry-save data, and correction constant scheme to eliminate sign-extension in compression operation of multiple partial multiplication results. The arithmetic unit has about 300-MHz operating frequency and about 37,000 gates on 45nm CMOS technology and its estimated performance is 300 MCOPS(Million Complex Operations Per Second). Because the arithmetic unit has high processing rate and supports a number of operations dedicated to various applications, it can be efficiently applicable to multimedia processors.

• Journal of the Korean Society for Nondestructive Testing
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• 제31권4호
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• pp.343-350
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• 2011

Recently, as the catastrophic disasters due to earthquake happen frequently all over the world, it draws lots of attention to seismic capacity evaluation and/or structural integrity assessment of deteriorated civil infra-structures. However, there have been few studies on the existing dam flood gates, expecially in Korea. In this study, a proper vibration testing method applicable to a dam flood gate has been suggested, since the dynamic characteristics of a darn flood gate can be fundamental data for seismic capacity evaluation or structural integrity assessment. The frequency domain decomposition technique has been incorporated for modal parameter identification. Two kinds of vibration tests using an impact hammer and ambient vibration sources were carried out on two types of dam floodgates with different shapes. Through the field tests, the effectiveness of the ambient vibration tests were verified.