• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.486-489
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• 2010

This paper describes a layered LDPC decoder which supports block length of 1,944 bits and code rate 1/2 for IEEE 802.11n WLAN standard. To reduce the hardware complexity, the min-sum algorithm and layered architecture is adopted. A novel memory reduction technique suitable for min-sum algorithm reduces memory size by 75% compared with conventional method. The designed processor has 200,400 gates and 19,400 bits memory, and it is verified by FPGA implementation. The estimated throughput is about 200 Mbps at 120 MHz clock by using Xilinx Virtex-4 FPGA device.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.12 no.2
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• pp.53-64
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• 2002

This paper describes a design of cryptographic processor that implements the AES (Advanced Encryption Standard) block cipher algorithm, "Rijndael". An iterative looping architecture using a single round block is adopted to minimize the hardware required. To achieve high throughput rate, a sub-pipeline stage is added by dividing the round function into two blocks, resulting that the second half of current round function and the first half of next round function are being simultaneously operated. The round block is implemented using 32-bit data path, so each sub-pipeline stage is executed for four clock cycles. The S-box, which is the dominant element of the round block in terms of required hardware resources, is designed using arithmetic circuit computing multiplicative inverse in GF($2^8$) rather than look-up table method, so that encryption and decryption can share the S-boxes. The round keys are generated by on-the-fly key scheduler. The crypto-processor designed in Verilog-HDL and synthesized using 0.25-$\mu\textrm{m}$ CMOS cell library consists of about 23,000 gates. Simulation results show that the critical path delay is about 8-ns and it can operate up to 120-MHz clock Sequency at 2.5-V supply. The designed core was verified using Xilinx FPGA board and test system.

• Nuclear Engineering and Technology
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• v.55 no.5
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• pp.1901-1910
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• 2023

The safety-class (1E) digital control system (DCS) of nuclear power plant characterized structural multiple redundancies, therefore, it is important to quantitatively evaluate the reliability of DCS in different degree of backup loss. In this paper, a reliability evaluation model based on T-S fuzzy fault tree (FT) is proposed for 1E DCS of nuclear power plant, in which the connection relationship between components is described by T-S fuzzy gates. Specifically, an output rejection control system is chosen as an example, based on the T-S fuzzy FT model, the key indicators such as probabilistic importance are calculated, and for a further discussion, the T-S fuzzy FT model is transformed into Bayesian Network(BN) equivalently, and the fault diagnosis based on probabilistic analysis is accomplished. Combined with the analysis of actual objects, the effectiveness of proposed method is proved.

• The KIPS Transactions:PartA
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• v.9A no.3
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• pp.271-280
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• 2002

In this paper, the input-output interconnection method of the multiple-valued signal processing circuit using Perfect Shuffle technique and Kronecker product is discussed. Using this method, the circuit design method of the multiple-valued Reed-Muller Expansions (MRME) which can process the multiple-valued signal easily on finite fields GF$(p^m)$ is presented. The proposed input-output interconnection methods show that the matrix transform is an efficient and the structures are modular. The circuits of multiple-valued signal processing of MRME on GF$(p^m)$ design the basic cells to implement the transform and inverse transform matrix of MRME by using two basic gates on GF(3) and interconnect these cells by the input-output interconnection technique of the multiple-valued signal processing circuits. The proposed multiple-valued signal processing circuits that are simple and regular for wire routing and possess the properties of concurrency and modularity are suitable for VLSI.

• Journal of the Korean Society of Safety
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• v.21 no.5 s.77
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• pp.22-27
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• 2006

Even though the interior of urban transit vehicle has been changed as a preventing measure against fire to make it inflammable, there remains a possibility of fire breaking out in case of gasoline etc being brought in the subway. However, there is also the possibility that in case if fire toxic gas is generated and hot air spreads in carriage it will prove very dangerous for people sitting inside. This is a comparative study where we compare simulation results with model examining the time and direction the fire spreads when it breaks out. Also there is vertical distribution of temperature in carriage where the fire spreads out. This study is about demonstrating how to establish smokeless system in urban vehicle, about its necessity, and about vehicle system restructuring. This study also makes an effort to find more advanced method for efficient fire safety in trains. In existing vehicles, in case of fire, the smoke can't go out when doors are closed and hence it spreads in whole train. Even though the method of using ventilation or exhaust established inside the carriage to throw smoke out is much better than the way of opening end doors in each carriage, this study is trying to do research on second way. Through simulation we see that in second case, even though not as good as the first one, smoke can exit through gates. Even though the first method is better, the second can also be uses to let fire out. We can know that in the first case as the smoke can exit out faster, it provides more safety for people. So this system provides better fire safety condition.

• Restorative Dentistry and Endodontics
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• v.19 no.2
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• pp.461-472
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• 1994

The purpose of this study was to evaluate the sealing ability according to types of spreader and compatibility of accessory cone used in lateral condensation method. 120 plastic blocks with canal preformed were instrumented with K-,H-files and Gates-Gllidden bur. Shaped plastic blocks were divided into six experimental groups according to spreader and accessory cone used in lateral condensation. Then they were obturated by lateral condensation method without -sealer. Six experimental groups were as follows: Group 1 : Filling with #30 spreader & #25 gutta-percha cone Group 2 : Filling with #30 spreader & Fine accessory cone Group 3 : Filling with #3 spreader & #25 gutta-percha cone Group 4 : Filling with #3 spreader & Fine accessory cone Group 5 : Filling with #20,#30 spreader & #25 gutta-percha cone Group 6 : Filling with #2, #3 spreader & Fine accessory cone All the blocks were stored in 100% humidor at room temperature for 2 days. Each block was placed in centrifuged for 20 minutes at 3,000 rpm. Apical leakage was mesured from the apical foramen to the most coronal level of- dye leakage in millimeter under a stereoscope. The data were analysed by ANOVA. The obtained results were as follows; 1. In groups using two spreaders(Group 5,6), the linear leakage was less than one spreader using groups(Group 1-4). 2. Tn groups using two spreaders(Group 5,6), there was no significant difference in linear leakage between standardized -spreader group and non standardized group (p>0.01). 3. When one spreader was used(Group 1-4), standardized-spreader groups showed less linear leakage than nonstandardized spreader groups(P<0.01). 4. In case of using same spreader(Groupl,2 & Group 3,4), there was no significant difference in linear leakage according to accessory cone type. 5. It needs to use one more spreaders to increase apical sealability.

• Journal of the Institute of Convergence Signal Processing
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• v.11 no.3
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• pp.244-249
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• 2010

The design of error correction code with low complexity has a good attraction for next generation multi-level cell flash memory. Sharing sub-expressions is effective method to reduce complexity and chip size. This paper proposes a new design method of m-bit parallel BCH encoder based on serial linear feedback shift register structure with low complexity using sub-expression. In addition, general algorithm for obtaining the sub-expression is introduced. The sub-expression can be expressed by matrix operation between sub-matrix of generator matrix and sum of two different variables. The number of the sub-expression is restricted by. The obtained sub-expressions can be shared for implementation of different m-parallel BCH encoder. This paper is not focused on solving a problem (delay) induced by numerous fan-out, but complexity reduction, expecially the number of gates.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.6
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• pp.55-66
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• 2016

Power gating is one of effective techniques for reducing leakage current in semiconductor chip. However, power gating cell (PGC) which is used to switch the power source causes performance degradation and the associated reliability problem by increasing IR drop. However, the newly raised problem caused by different scaling properties between gates and metal wires demands additional considerations in power gating design. In this paper, we propose a robust cell placement based power gating design method for reducing the area for power gating cell and metal routing thus to meet IR drop requirement. Experimental results by applying the proposed techniques on the application processor for smartphone fabricated in 28nm CMOS process show that power gating cell area is reduced by 16.16% and maximum IR drop value is also decreased by 8.49% compared to existing power gating cell placement techniques.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.15 no.4
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• pp.2460-2468
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• 2014

A local rain that is concentrated in specific area in a short time frequently occurs due to recent abnormal weather. To prevent potential flood disasters, therefore, it is necessary to be established to the flood control system. Checking the river design standard, however, hydrologic design frequency of water gate is only marked as over 20 years, so this fact shows that the standard is unclear. The inland inundation modeling considering the stage in a river and quantitative assessment are required to reduce flood damage. The simulation for internal inundation is very complex and is time-consuming due to considering hydraulic hydrology characteristics at the same time. Using the already established river master plan, consequently, this study proposed the simple and convenient method for assessment of the internal inundation simulation. Using the proposed method in the upper and middle regions of a river, influences for design frequency or water gate location were assessed by applying the nine probability precipitation with design frequency and by targeting the water gates which are installed in five inlands.

• Journal of Oriental Neuropsychiatry
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• v.9 no.2
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• pp.45-51
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• 1998

Purpose : This study has an experiment on finding how Hyangbujapamultang advanced the learning and memory of rat to find the method to improve the failure of memory which is the symptom of dementia.Method : In the experiment, rats were divided the control group (14 rat) which medicate the excipient into the sample group (17 rat) which medicates Hyangbujapalmutang. And the learning ability test and the memorv test was practiced to using the task of radial arm maze.The learning ability test had the presupposition that, when a rat which frequents 8 tracks makes am error not exceeding one time for 3 days without a break, it passes the test.First experiment compared total days when the control group passed the test with total days when the sample group it.The memory test practiced after 24 hours when the learning ability test was over. When a rat frequents 4 tracks, the gates is cut off during 30 seconds. Here the number of error at the control group with that of the sample group.Result: In the learning ability test, the sample group needed 5.82${\pm}$0.37 days to pass the test and the control group needed 6.43${\pm}$0.67 days. In the memory test, the sample group errored 0.29${\pm}$0.37 times and the control group errored 1.86${\pm}$0.78 times.Conclusion : In the learning ability test, the sample group passed the test earlier than the control group, but any statistical correlationship couldn't be found in it. In the memory test, the sample group had the pregnant reduction of the number of error in comparison with the control group.