• Polymer(Korea)
• /
• v.25 no.6
• /
• pp.855-865
• /
• 2001

The optimization condition of injection molding for a commercial product of TV speaker grille of A Company was induced using a CAE software of Moldflow. The flow and packing phase analysis was performed by using flow balance, runner balance, and the intermediate one by using the above two balances, which were used for controlling the amount of packing resins into the cavity, Later, the analysis performed by using the measured viscosity (local database) at various shear rates and the results were compared with the computer simulation using the standard database. Flow balance induced minimized weld line resulted in a better appearance and physical properties of the were line, but exhibited a disadvantage of large deformation and gas formation due to over-packing of the molten resin in the center of the speaker grille. Runner balance improved the disadvantage of the flow balance by controlling the amount of molten resin injected from the gate, however resulted reduced mechanical properties and poor appearance of the weld line. However, the modified method induced from the flow and runner balance improved the disadvantages by changing the runner size. In addition, the analyses based on the local database and the standard database were compared. Although the measured viscosity was slightly higher and the temperature distribution was broader than the standard database, no distinct difference was obtained from the analysis using the two different databases.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.14 no.1
• /
• pp.183-190
• /
• 2010

We propose an eFuse one-time programmable (OTP) memory cell based on a logic process, which is programmable by an external program voltage. For the conventional eFuse OTP memory cell, a program datum is provided with the SL (Source Line) connected to the anode of the eFuse going through a voltage drop of the SL driving circuit. In contrast, the gate of the NMOS program transistor is provided with a program datum and the anode of the eFuse with an external program voltage (FSOURCE) of 3.8V without any voltage drop for the newly proposed eFuse cell. The FSOURCE voltage of the proposed cell keeps either 0V or the floating state at read mode. We propose a clamp circuit for being biased to 0V when the voltage of FSOURCE is in the floating state. In addition, we propose a VPP switching circuit switching between the logic VDD (=1.8V) and the FSOURCE voltage. The layout size of the designed eFuse OTP memory IP with Dongbu HiTek's $0.15{\mu}m$ generic process is $359.92{\times}90.98{\mu}m^2$.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.47 no.5
• /
• pp.71-79
• /
• 2010

This paper presents a design of a LLC resonant controller IC. LLC resonant controller IC controls the voltage of the 2nd side by adjusting frequency the input frequency of the external resonant circuit. The clock generator is integrated to provide the pulse to the resonant circuit and its frequency is controlled by the external resistor. Also, the frequency of the VCO is adjusted by the feedback voltage. The protection circuits such as UVLO(Under Voltage Lock Out), brown out, fault detector are implemented for the reliable and stable operation. The HVG, and LVG drivers can provide the high current and voltage to the IGBT. The designed LLC resonant controller IC is fabricated with the 0.35 um 2P3M BCD process. The overall die size is $1400um{\times}1450um$, and supply voltage is 5V, 15V.

• Journal of architectural history
• /
• v.16 no.3
• /
• pp.75-94
• /
• 2007

There were many researches on marine transportation and granaries, most of which focused on the historical establishment and organization of the marine transportation. However, a few researches were conducted on the architectural aspects. Hence the purposes of this study are to investigate the following matters: first, documents and relics concerning the tribute granary castle at Cape Gongse in Asan, a typical granary during the Joseon Dynasty, were investigated to academically understand the castle's establishment and historical background; second, the dispositional characteristics of the granary and the castle, including its adjacent facilities, were investigated to review its archaeological value; finally, basic materials were provided for systematical preservation and management these relics. As for the research method, the author referred to and analyzed sundry records and old maps, and ascertained in detail historical evidence through residential testimonies and the on-the-spot surveys. In addition, the author investigated the dispositional characteristics of the tribute granary castle at Cape Gongse by analyzing its exact size and shape, based on the old documents and an actual survey of the castle remains. The characteristics of the tribute granary castle at Cape Gongse may be summarized as follows. First, tribute granary at cape Gongse is a only tribute granary which has a granary and castle. second, the tribute granary castle at Cape Gongse has a curvilinear shape, like a gourd dipper; a large circle surrounding the village and a small circle surrounding the area of Mt. Shinpoong both meet up with it. Third, the construction type of the tribute granary castle at Cape Gongse is in a style similar to a town castle or a battle camp castle located in the coastal regions. As for its locational conditions, however, the east gate, presumably an incoming and outgoing route to the granary for vessels, was a feature unique to the marine granary castle. Fourth, the tribute granary at Cape Gongse had a granary of eighty kan in 1523 and, in addition, there were also Bongsang-cheong, Sa-chang, Joseon-sobakcheo, Chimhae-dang, and more, not to mention many privates houses in the castle. The granary is located in the center of the tribute granary castle, where Gongse Nonghyub is currently located. The location of the government offices seemed to be on the northern ridge. Fifth, the tribute granary castle at Cape Gongse is a valuable relic that offers insight into marine transportation, tribute granaries, and tribute granary castles during the Joseon Dynasty. It has special archaeological value because it was one of only a few tribute granary castles that served to protect the tribute granaries.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.40 no.6
• /
• pp.431-441
• /
• 2003

This paper presents the design of 32 bit microprocessor for a sequence control using a field programmable gate array(FPGA). The microprocessor was designed by a VHDL with top down method, the program memory was separated from the data memory for high speed execution of sequence instructions. Therefore it was possible that sequence instructions could be operated at the same time during the instruction fetch cycle. In order to reduce the instruction decoding time and the interface time of the data memory interface, an instruction code size was implemented by 32 bits. And the real time debug operation was implemented for easeful debugging the designed processor with a single step run, PC break point run, data memory break point run. Also in this designed microprocessor, pulse instructions, step controllers, master controllers, BM and BCD type arithmetic instructions, barrel shift instructions were implemented for sequence logic control. The FPGA was synthesized under a Xilinx's Foundation 4.2i Project Manager using a V600EHQ240 which contains 600,000 gates. Finally simulation and experiment were successfully performed respectively. For showing good performance, the designed microprocessor for the sequence logic control was compared with the H8S/2148 microprocessor which contained many bit instructions for sequence logic control. The designed processor for the sequence logic showed good performance.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.38 no.11
• /
• pp.63-70
• /
• 2001

We demonstrate the MMIC (monolithic microwave integrated circuit) frequency doublers generating stable and low-cost 29 GHz local oscillator signals from 14.5 GHz input signals. These devices were designed and fabricated by using the M MIC integration process of $0.1\;{\mu}m$ gate-length PHEMTs (pseudomorphic high electron mobility transistors) and passive components. The measurements showed S11 or -9.2 dB at 145 GHz, S22 of -18.6 dG at 29 GHz and a minimum conversion loss of 18.2 dB at 14.5 GHz with an input power or 6 dBm. Fundamental signal of 14.5 GHz were suppressed below 15.2 dBe compared to the second harmonic signal at the output port, and the isolation characteristics of fundamental signal between the input and the output port were maintained above :i0 dB in the frequency range 10.5 GHz to 18.5 GHz. The chip size of the fabricated MMIC frequency doubler is $1.5{\times}2.2\;mm^2$.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.49 no.10
• /
• pp.111-121
• /
• 2012

In this paper, a poly-Si thin film transistor with ${\sim}0.5{\mu}m$ gate length was fabricated and its electrical characteristics are optimized. From the results, it was verified that making active region with larger grain size using low temperature annealing is an efficient way to enhance the subthreshold swing, drain-induced barrier lowering and on-current characteristics. A SONOS flash memory was fabricated using this poly-Si channel process and its performances are analyzed. It was necessary to optimize O/N/O thickness for the reduction of electron back tunneling and the enhancement of its memory operation. The optimized device showed 2.24 V of threshold voltage memory windows which coincided with a well operating flash memory.

• Journal of Sensor Science and Technology
• /
• v.12 no.2
• /
• pp.72-78
• /
• 2003

To observe the effect of excitation coil pitch on the micro fluxgate magnetic sensor, two sensors are fabricated using multi layer board process and the pitch distance of excitation coil are $260\;{\mu}m$ and $520\;{\mu}m$, respectively. The fluxgate sensor consists of five PCB stack layers including one layer of magnetic core and four layers of excitation and pick-up coils. The center layer as magnetic core is made of a Co-based amorphous magnetic ribbon with extremely high DC permeability of ${\sim}100,000$ and has a rectangular-ring shape to minimize the magnetic flux leakage. Four outer layers as excitation and pick-up coils have a planar solenoid structure and are made of copper foil. In case of the fluxgate sensor having the excitation coil pitch of $260\;{\mu}m$, excellent linear response over the range of $-100\;{\mu}T$ to $+100\;{\mu}T$ is obtained with sensitivity of 780 V/T at excitation sine wave of $3V_{p_p}$ and 360 kHz. The chip size of the fabricated sensing element is $7.3\;{\times}\;5.7\;mm^2$. The very low power consumption of ${\sim}8\;mW$ is measured. This magnetic sensor is very useful for various applications such as: portable navigation systems, telematics, VR game and so on.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.22 no.6
• /
• pp.584-597
• /
• 2011

In this paper, low-loss and high-power RF SP6T switch chips are designed, fabricated and measured for GSM/EGSM/DCS/PCS applications using WIN Semiconductors 0.5 ${\mu}m$ pHEMT process. We utilized a combined configuration of series and series-shunt structures for optimized switch performance, and a common transistor structure on a receiver path for reducing chip area. The gate width and the number of stacked transistors are determined using ON/OFF input power level of the transceiver system. To improve the switch performance, feed-forward capacitors, shunt capacitors and parasitic FET inductance elimination due to resonance are actively used. The fabricated chip size is $1.2{\times}1.5\;mm^2$. S-parameter measurement shows an insertion loss of 0.5~1.2 dB and isolation of 28~36 dB. The fabricated SP6T switch chips can handle 4 W input power and suppress second and third harmonics by more than 75 dBc.

• Journal of the Semiconductor & Display Technology
• /
• v.6 no.3
• /
• pp.19-23
• /
• 2007

The NiSi is very promising candidate for the metallization in 45 nm CMOS process such as FUSI(fully silicided) gate and source/drain contact because it exhibits non-size dependent resistance, low silicon consumption and mid-gap workfunction. Ni film was first deposited by using ALD (atomic layer deposition) technique with Bis-Ni precursor and $H_2$ reactant gas at $220^{\circ}C$ with deposition rate of $1.25\;{\AA}/cycle$. The as-deposited Ni film exhibited a sheet resistance of $5\;{\Omega}/{\square}$. RTP (repaid thermal process) was then performed by varying temperature from $400^{\circ}C$ to $900^{\circ}C$ in $N_2$ ambient for the formation of NiSi. The process temperature window for the formation of low-resistance NiSi was estimated from $600^{\circ}C$ to $800^{\circ}C$ and from $700^{\circ}C$ to $800^{\circ}C$ with and without Ti capping layer. The respective sheet resistance of the films was changed to $2.5\;{\Omega}/{\square}$ and $3\;{\Omega}/{\square}$ after silicidation. This is because Ti capping layer increases reaction between Ni and Si and suppresses the oxidation and impurity incorporation into Ni film during silicidation process. The NiSi films were treated by additional thermal stress in a resistively heated furnace for test of thermal stability, showing that the film heat-treated at $800^{\circ}C$ was more stable than that at $700^{\circ}C$ due to better crystallinity.