• Korean Journal of Heritage: History & Science
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• v.55 no.1
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• pp.265-280
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• 2022

Hwangnyongsa Temple was the large Buddhist monastery of Silla that has existed for about 685 years. The temple underwent a series of excavations from 1976 to 1983, during which it was discovered that its layout consisted of one pagoda and three main dharma halls. This discovery also led to the production of four artistic depictions of the temple at various times from its foundation to its final phase. Previous studies on the architectural layout of Hwangnyongsa Temple are largely focused on the inner sanctuary ("Buddha's Land"). The studies on the temple's main architectural structures may be natural for those who are interested in the origins of and background to its establishment, but the studies on its outer sanctuary ("Sangha's Land") have to come first to acquire a deeper knowledge of the architectural layout of the temple as a whole. To gain a comprehensive understanding of the entire layout of Buddhist monasteries of the Silla dynasty, including both their inner and outer sanctuaries, the studies on Hwangnyongsa Temple are essential as it was once the kingdom's most highly honored temple. The studies on Korean Buddhist monasteries of the Three Kingdoms Period have produced only a limited amount of information concerning the outer sanctuary, resulting in little evidence about the exact scope of the temple's sanctuary. Meanwhile, the excavations of the Hwangnyongsa Temple site have revealed the archaeological features of the walls that divided the monastery and its neighboring facilities, thus helping to delineate the size of the temple site. The excavations have revealed the boundaries between the inner and outer sanctuaries of Hwangnyongsa Temple, as well as the entire temple precincts and the exterior, providing valuable information about the changes made to the layout of the temple. In this study, the main discussion focuses on the changes made to the sanctuary of Hwangnyongsa Temple during the Unified Silla and Goryeo Periods, particularly in relation to the architectural layout of the temple. The discussion is based on a review of the periods in which the Nammunji(South Gate site) was built, which provides tangible evidence about the expansion of the temple to the south, and the walls enclosing the temple precincts on the four sides and the changes that occurred afterwards. As a result, the study concludes that both the inner and outer sanctuaries of the temple probably changed through the 1 st and 3rd. It also concludes that the changes made to the architectural layout of Hwangnyongsa Temple were intended not only to alter the scope of the temple but were also closely associated with the politico-geographical significance of its location at the center of the royal capital of Silla and the urban archaeological remains around it.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.9C
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• pp.861-870
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• 2002

In this paper, with targeting on the drawback of RSA of operation speed, a new 1024-bit RSA cryptosystem has been proposed and implemented in hardware to increase the operational speed and perform the variable-length encryption. The proposed cryptosystem mainly consists of the modular exponentiation part and the modular multiplication part. For the modular exponentiation, the RL-binary method, which performs squaring and modular multiplying in parallel, was improved, and then applied. And 4-stage CSA structure and radix-4 booth algorithm were applied to enhance the variable-length operation and reduce the number of partial product in modular multiplication arithmetic. The proposed RSA cryptosystem which can calculate at most 1024 bits at a tittle was mapped into the integrated circuit using the Hynix Phantom Cell Library for Hynix 0.35㎛ 2-Poly 4-Metal CMOS process. Also, the result of software implementation, which had been programmed prior to the hardware research, has been used to verify the operation of the hardware system. The size of the result from the hardware implementation was about 190k gate count and the operational clock frequency was 150㎒. By considering a variable-length of modulus number, the baud rate of the proposed scheme is one and half times faster than the previous works. Therefore, the proposed high speed variable-length RSA cryptosystem should be able to be used in various information security system which requires high speed operation.

• Journal of the Korean Society of Marine Environment & Safety
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• v.19 no.4
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• pp.345-351
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• 2013

The IWRAP program (Inland Waterway Risk Assessment Program) is a useful program for risk assessment of a waterway. However, in the basic version, the function which is used to import AIS data is not included. So users have to prepare the data and input to the program manually. And not all waterways have enough statistical data about passing vessels especially in developing countries as Vietnam. This paper studies the development of a program to pre-process AIS data for using the IWRAP Mk2 program basic version. In addition, it provides users basic information about marine traffic in a waterway such as routes layout, number of passages at a gate classified by type, size and time. The developed program, named TOAIS (Total AIS), was successfully used to pre-process AIS data collected in the Vung Tau waterway-Vietnam. As a result, the IWRAP Mk2 program basic version using data pre-processed from TOAIS could effectively assess the risk of collision in this waterway.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.8
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• pp.39-48
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• 2016

In this paper, we propose thermal resistance compact model of FinFET structure that has hexagon shaped source/drain. The heating effect and thermal properties were increased by reduced size of the device, and thermal resistance is an important factor to analyze the effect and the properties. The heat source and each contact that is moved heat out were set up in transistor, and domain is divided by the heat source and the four parts of contacts : source, drain, gate, substrate. Each contact thermal resistance model is subdivided as a easily interpretable structure by analyzing the temperature and heat flow of the TCAD simulation results. The domains are modeled based on an integration or conformal mapping method through the structure parameters according to its structure. First modeled by analyzing the thermal resistance to a single fin, and applying the change in the parameter of the channel increases to improve the accuracy of the thermal resistance model of the multi-fin/ finger. The proposed thermal resistance model was compared to the thermal resistance by analyzing results of the 3D Technology CAD simulations, and the proposed total thermal resistance model has an error of 3 % less in single and multi-finl. The proposed thermal resistance model can predict the thermal resistance due to the increase of the fin / finger, and the circuit characteristics can be improved by calculating the self-heating effect and thermal characterization.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.7
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• pp.1296-1302
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• 2016

A hardware implementation of ultra-lightweight block cipher algorithm PRESENT that was specified as a block cipher standard for lightweight cryptography ISO/IEC 29192-2 is described in this paper. Two types of crypto-core that support master key size of 80-bit are designed, one is for encryption-only function, and the other is for encryption and decryption functions. The designed PR80 crypto-cores implement the basic cipher mode of operation ECB (electronic code book), and it can process consecutive blocks of plaintext/ciphertext without reloading master key. The PR80 crypto-cores were designed in soft IP with Verilog HDL, and they were verified using Virtex5 FPGA device. The synthesis results using $0.18{\mu}m$ CMOS cell library show that the encryption-only core has 2,990 GE and the encryption/decryption core has 3,687 GE, so they are very suitable for IoT security applications requiring small gate count. The estimated maximum clock frequency is 500 MHz for the encryption-only core and 444 MHz for the encryption/decryption core.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.16 no.12
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• pp.8643-8648
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• 2015

In this paper presents the design and demonstrate 8 W 3-stage HPA(High Power Amplifier) MMIC(Monolithic Microwave Integrated Circuits) for Ka-band down link satellite communications payload system at 19.5 GHz ~ 22 GHz frequency band. The HPA MMIC consist of 3-stage GaN HEMT(Hight Electron Mobility Transistors). The gate periphery of $1^{st}$ stage, $2^{nd}$ stage and output stage is determined $8{\times}50{\times}2$ um, $8{\times}50{\times}4$ um and $8{\times}50{\times}8$ um, respectively. The fabricated HPA MMIC shows size $3,400{\times}3,200um^2$, small signal gain over 29.6 dB, input matching -8.2 dB, output matching -9.7 dB, output power 39.1 dBm and PAE 25.3 % by using 0.15 um GaN technology at 20 V supply voltage in 19.5~22 GHz frequency band. Therefore, this HPA MMIC is believed to be adaptable Ka-band satellite communication payloads down link system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.1
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• pp.22-30
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• 2011

In this paper, we propose a memory efficient multi-rate Low Density Parity Check (LDPC) decoder for China Mobile Multimedia Broadcasting (CMMB). We find the best trade-off between the performance and the circuit area by designing a partially parallel decoder which is capable of passing multiple messages in parallel. By designing an efficient address generation unit (AGU) with an index matrix, we could reduce both the amount of memory requirement and the complexity of computation. The proposed regular LDPC decoder was designed in Verilog HDL and was synthesized by Synopsys' Design Compiler using Chartered $0.18{\mu}m$ CMOS cell library. The synthesized design has the gate size of 455K (in NAND2). For the two code rates supported by CMMB, the rate-1/2 decoder has a throughput of 14.32 Mbps, and the rate-3/4 decoder has a throughput of 26.97 Mbps. Compared with a conventional LDPC for CMMB, our proposed design requires only 0.39% of the memory.

• Journal of Nuclear Fuel Cycle and Waste Technology(JNFCWT)
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• v.4 no.2
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• pp.161-170
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• 2006

PFC(Perfluorocarbon) decontamination process is one of best methods to remove hot particulate adhered on the inner surface of hot cell and surface of equipment in hot cell. It was necessary to develop a filtration equipment to reuse the PFC waste solution generated on PFC decontamination due to the high cost of PFC solution and for minimization of the volume of second waste solution. The filtration equipment was developed to remove hot particulate in PFC waste solution. It was made suitable size and weight in consideration of hot cell gate and crane. And it has wheels for easy movement. Flux of the filtration equipment decreased with particulate concentration increase. It consists of pre-filter($1.4{\mu}m$) and final-filter($0.2{\mu}m$) for protection of the flux decrease along filtration time. It treatment capacity of waste solution is 0.2 L/min.

• Journal of Korea Multimedia Society
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• v.6 no.3
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• pp.444-454
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• 2003

An analysis of heart movement is to estimate a role which supplies blood in human body. We have constructed a left ventricle myocardium model and mathematically evaluated the motion of myocardium. The myocardial motility was visualized using some parameters about cardiac motion. We applied the myocardium model in the gated myocardium SPECT image that showed a cardiac biochemical reaction, and analyzed a motility between the gated myocardium SPECT image and the myocardium model. The myocardium model was created of the based on three dimensional super-ellipsoidal model that was using the sinusoidal function. To express a similar form and motion of the left ventricle myocardium, we calculated parameter functions that gave the changing of motion and form. The LSF algorithm was applied to the myocardium gated SPECT image data and the myocardium model, and finally created a fitting model. Then we analyzed a regional motility direction and size of the gated myocardium SPECT image that was constructed on a fitting model. Furthermore, we implemented the Bull's Eye map that had evaluated the heart function for presentation of regional motility. Using myocardium's motion the evaluation of cardiac function of SPECT was estimated by a contraction ability, perfusion etc. However, it is not any estimation about motility. So, We analyzed the myocardium SPECT's motility of utilizing the myocardium model. We expect that the proposed algorithm should be a useful guideline in the heart functional estimation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.7
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• pp.1332-1339
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• 2001

SoC(System on Chip) technology is widely used in the field of embedded systems by providing high flexibility for a specific application domain. An important aspect of development any new embedded system is verification which usually requires lengthy software and hardware co-design. To reduce development cost of design effort, the instruction set of microprocessor must be suitable for a high level language compiler. And FPGA prototype system could be derived and tested for design verification. In this paper, we propose a 16 bit FPGA microprocessor, which is tentatively-named EISC16, based on an EISC(Extendable Instruction Set Computer) architecture for embedded applications. The proposed EISC16 has a 16 bit fixed length instruction set which has the short length offset and small immediate operand. A 16 bit offset and immediate operand could be extended using by an extension register and an extension flag. We developed a cross C/C++ compiler and development software of the EISC16 by porting GNU on an IBM-PC and SUN workstation and compared the object code size created after compiling a C/C. standard library, concluding that EISC16 exhibits a higher code density than existing 16 microprocessors. The proposed EISC16 requires approximately 6,000 gates when designed and synthesized with RTL level VHDL at Xilinix's Virtex XCV300 FPGA. And we design a test board which consists of EISC16 ROM, RAM, LED/LCD panel, periodic timer, input key pad and RS-232C controller. 11 works normally at 7MHz Clock.