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Development of Chip-based Precision Motion Controller

  • Cho, Jung-Uk;Jeon, Jae-Wook
    • 제어로봇시스템학회:학술대회논문집
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    • 2003.10a
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    • pp.1022-1027
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    • 2003
  • The Motion controllers provide the sophisticated performance and enhanced capabilities we can see in the movements of robotic systems. Several types of motion controllers are available, some based on the kind of overall control system in use. PLC (Programmable Logic Controller)-based motion controllers still predominate. The many peoples use MCU (Micro Controller Unit)-based board level motion controllers and will continue to in the near-term future. These motion controllers control a variety motor system like robotic systems. Generally, They consist of large and complex circuits. PLC-based motion controller consists of high performance PLC, development tool, and application specific software. It can be cause to generate several problems that are large size and space, much cabling, and additional high coasts. MCU-based motion controller consists of memories like ROM and RAM, I/O interface ports, and decoder in order to operate MCU. Additionally, it needs DPRAM to communicate with host PC, counter to get position information of motor by using encoder signal, additional circuits to control servo, and application specific software to generate a various velocity profiles. It can be causes to generate several problems that are overall system complexity, large size and space, much cabling, large power consumption and additional high costs. Also, it needs much times to calculate velocity profile because of generating by software method and don't generate various velocity profiles like arbitrary velocity profile. Therefore, It is hard to generate expected various velocity profiles. And further, to embed real-time OS (Operating System) is considered for more reliable motion control. In this paper, the structure of chip-based precision motion controller is proposed to solve above-mentioned problems of control systems. This proposed motion controller is designed with a FPGA (Field Programmable Gate Arrays) by using the VHDL (Very high speed integrated circuit Hardware Description Language) and Handel-C that is program language for deign hardware. This motion controller consists of Velocity Profile Generator (VPG) part to generate expected various velocity profiles, PCI Interface part to communicate with host PC, Feedback Counter part to get position information by using encoder signal, Clock Generator to generate expected various clock signal, Controller part to control position of motor with generated velocity profile and position information, and Data Converter part to convert and transmit compatible data to D/A converter.

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SOI CMOS Miniaturized Tunable Bandpass Filter with Two Transmission zeros for High Power Application (고 출력 응용을 위한 2개의 전송영점을 가지는 최소화된 SOI CMOS 가변 대역 통과 여파기)

  • Im, Dokyung;Im, Donggu
    • Journal of the Institute of Electronics and Information Engineers
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    • v.50 no.1
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    • pp.174-179
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    • 2013
  • This paper presents a capacitor loaded tunable bandpass chip filter using multiple split ring resonators (MSRRs) with two transmission zeros. To obtain high selectivity and minimize the chip size, asymmetric feed lines are adopted to make a pair of transmission zeros located on each side of passband. Compared with conventional filters using cross-coupling or source-load coupling techniques, the proposed filter uses only two resonators to achieve high selectivity through a pair of transmission zeros. In order to optimize selectivity and sensitivity (insertion loss) of the filter, the effect of the position of asymmetric feed line on transmission zeros and insertion loss is analyzed. The SOI-CMOS switched capacitor composed of metal-insulator-metal (MIM) capacitor and stacked-FETs is loaded at outer rings of MSRRs to tune passband frequency and handle high power signal up to +30 dBm. By turning on or off the gate of the transistors, the passband frequency can be shifted from 4GH to 5GHz. The proposed on-chip filter is implemented in 0.18-${\mu}m$ SOI CMOS technology that makes it possible to integrate high-Q passive devices and stacked-FETs. The designed filter shows miniaturized size of only $4mm{\times}2mm$ (i.e., $0.177{\lambda}g{\times}0.088{\lambda}g$), where ${\lambda}g$ denotes the guided wave length of the $50{\Omega}$ microstrip line at center frequency. The measured insertion loss (S21)is about 5.1dB and 6.9dB at 5.4GHz and 4.5GHz, respectively. The designed filter shows out-of-band rejection greater than 20dB at 500MHz offset from center frequency.

A Unified ARIA-AES Cryptographic Processor Supporting Four Modes of Operation and 128/256-bit Key Lengths (4가지 운영모드와 128/256-비트 키 길이를 지원하는 ARIA-AES 통합 암호 프로세서)

  • Kim, Ki-Bbeum;Shin, Kyung-Wook
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.21 no.4
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    • pp.795-803
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    • 2017
  • This paper describes a dual-standard cryptographic processor that efficiently integrates two block ciphers ARIA and AES into a unified hardware. The ARIA-AES crypto-processor was designed to support 128-b and 256-b key sizes, as well as four modes of operation including ECB, CBC, OFB, and CTR. Based on the common characteristics of ARIA and AES algorithms, our design was optimized by sharing hardware resources in substitution layer and in diffusion layer. It has on-the-fly key scheduler to process consecutive blocks of plaintext/ciphertext without reloading key. The ARIA-AES crypto-processor that was implemented with a $0.18{\mu}m$ CMOS cell library occupies 54,658 gate equivalents (GEs), and it can operate up to 95 MHz clock frequency. The estimated throughputs at 80 MHz clock frequency are 787 Mbps, 602 Mbps for ARIA with key size of 128-b, 256-b, respectively. In AES mode, it has throughputs of 930 Mbps, 682 Mbps for key size of 128-b, 256-b, respectively. The dual-standard crypto-processor was verified by FPGA implementation using Virtex5 device.

8×8 HEVC Inverse Core Transform Architecture Using Multiplier Reuse (곱셈기를 재사용하는 8×8 HEVC 코어 역변환기 설계)

  • Lee, Jong-Bae;Lee, Seongsoo
    • Journal of IKEEE
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    • v.17 no.4
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    • pp.570-578
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    • 2013
  • This paper proposed an $8{\times}8$ HEVC inverse core transform architecture reusing multipliers. In HEVC core transform, processing of lower size block is identical with even part of upper size block. So an $8{\times}8$ core transform architecture can process both $8{\times}8$ and $4{\times}4$ core transforms. However, when $8{\times}8$ core transform architecture is exploited, frame processing time doubles in $4{\times}4$ core transform, since $8{\times}8$ and $4{\times}4$ core transforms concurrently process 8 and 4 pixels, respectively. In this paper, a novel inverse core transform architecture is proposed based on multiplier reuse. It runs as an $8{\times}8$ inverse core transformer or two $4{\times}4$ inverse core transformer. Its frame processing time is same in $8{\times}8$ and $4{\times}4$ core transforms, and reduces gate counts by 12%.

Analysis of the Threshold Voltage Instability of Bottom-Gated ZnO TFTs with Low-Frequency Noise Measurements (Low-Frequency Noise 측정을 통한 Bottom-Gated ZnO TFT의 문턱전압 불안정성 연구)

  • Jeong, Kwang-Seok;Kim, Young-Su;Park, Jeong-Gyu;Yang, Seung-Dong;Kim, Yu-Mi;Yun, Ho-Jin;Han, In-Shik;Lee, Hi-Deok;Lee, Ga-Won
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.23 no.7
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    • pp.545-549
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    • 2010
  • Low-frequency noise (1/f noise) has been measured in order to analyze the Vth instability of ZnO TFTs having two different active layer thicknesses of 40 nm and 80 nm. Under electrical stress, it was found that the TFTs with the active layer thickness of 80 nm shows smaller threshold voltage shift (${\Delta}V_{th}$) than those with thickness of 40 nm. However the ${\Delta}V_{th}$ is completely relaxed after the removal of DC stress. In order to investigate the cause of this threshold voltage instability, we accomplished the 1/f noise measurement and found that ZnO TFTs exposed the mobility fluctuation properties, in which the noise level increases as the gate bias rises and the normalized drain current noise level($S_{ID}/{I_D}^2$) of the active layer of thickness 80 nm is smaller than that of active layer thickness of thickness 40 nm. This result means that the 80 nm thickness TFTs have a smaller density of traps. This result correlated with the physical characteristics analysis performmed using XRD, which indicated that the grain size increases when the active layer thickness is made thicker. Consequently, the number of preexisting traps in the device increases with decreasing thickness of the active layer and are related closely to the $V_{th}$ instability under electrical stress.

A Study on the Development of Remodeling (plan) by Deriving Temporary House Improvements (임시주거용 조립주택 개선사항 도출을 통한 리모델링(안) 개발 연구)

  • Lee, Ji-Hyang;Son, Myung-Chan;Kwon, Jin-Suk;Park, Sang-Hyun;Won, Jin-Yung
    • Journal of the Society of Disaster Information
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    • v.15 no.2
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    • pp.301-311
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    • 2019
  • Purpose and Method: In this study, a questionnaire interview survey was conducted for the victims living in the temporary house by the Pohang earthquake, and improvements were derived. Results: As a result, major improvements in terms of facilities are as follows. First, in order to expand the toilet and cooking space, the existing inner gate and the wall are removed and the width of the toilet is expanded. Minimize the inconvenience by adding a cooking table as wide as the extended toilet. Second, a separate sleep compartment is set up to secure storage space in a limited area. And the storage closet is installed below and used as a storage space. At this time, the size of the sleeping space is set to double bed size. Third, curtains and blinds are installed on both windows to secure privacy, thereby protecting privacy and psychological stability. Conclusion: If the remodeling of the temporary house proposed in this study is utilized and applied, it is possible to provide a better living environment. In addition, it is expected that it will be possible to improve the efficiency of space and overcome existing spatial limitations by minimizing inconveniences reflecting the needs of the victims.

Changes in sedimentary structure and elemental composition in the Nakdong Estuary, Korea (낙동강 하구역 퇴적구조 및 원소조성 변화에 관한 연구)

  • Kim, Yunji;Kang, Jeongwon;Park, Seonyoung
    • Journal of Wetlands Research
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    • v.23 no.3
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    • pp.213-223
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    • 2021
  • To understand the sedimentary environment of Scirpus planiculmis habitat (Myeongji and Eulsuk tidal flats) in the Nakdong Estuary, this study analyzed the statistical parameters (sorting, skewness, and kurtosis) of grain size data and the major (Al, Fe, Mn, Mg, Ca, Na, K, Ti, and P), minor (Li, Sc, V, Cr, Co, Ni, Cu, Zn, Sr, Zr, Cs, Pb, Th, and U), and rare earth elements (REEs) in sediment cores. For Myeongji, the sediment structure of the upper part of the cores was poorly sorted, more finely skewed, and more leptokurtic due to construction of the West gate. By contrast, the Eulsuk cores all differed due to the contrasting floodgate operation patterns of the West and East gates. The linear discriminate function (LDF) results corresponded to the statistical parameters for grain size. At the Eulsuk tidal flat (sites ES05 and ES11), elemental distributions were representative of Al-, Fe- and Ca-associated profiles, in which the elements are largely controlled by the accumulation of their host minerals (such as Na- and K-aluminosilicate and ferromagnesium silicate) and heavy detrital minerals at the sites. Detrital minerals including the aluminosilicates are major factors in the elemental compositions at ES05, diluting the REE contents. However, clay minerals and Fe-oxyhydroxides, as well as REE-enriched heavy minerals, appeared to be controlling factors of the elemental composition at ES11. Therefore, the mineral fractionation process is important in determining the elemental composition during sedimentation, which reflects the depositional condition of riverine-saline water mixing at both sites.

Estimation of Internal Motion for Quantitative Improvement of Lung Tumor in Small Animal (소동물 폐종양의 정량적 개선을 위한 내부 움직임 평가)

  • Yu, Jung-Woo;Woo, Sang-Keun;Lee, Yong-Jin;Kim, Kyeong-Min;Kim, Jin-Su;Lee, Kyo-Chul;Park, Sang-Jun;Yu, Ran-Ji;Kang, Joo-Hyun;Ji, Young-Hoon;Chung, Yong-Hyun;Kim, Byung-Il;Lim, Sang-Moo
    • Progress in Medical Physics
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    • v.22 no.3
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    • pp.140-147
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    • 2011
  • The purpose of this study was to estimate internal motion using molecular sieve for quantitative improvement of lung tumor and to localize lung tumor in the small animal PET image by evaluated data. Internal motion has been demonstrated in small animal lung region by molecular sieve contained radioactive substance. Molecular sieve for internal lung motion target was contained approximately 37 kBq Cu-64. The small animal PET images were obtained from Siemens Inveon scanner using external trigger system (BioVet). SD-Rat PET images were obtained at 60 min post injection of FDG 37 MBq/0.2 mL via tail vein for 20 min. Each line of response in the list-mode data was converted to sinogram gated frames (2~16 bin) by trigger signal obtained from BioVet. The sinogram data was reconstructed using OSEM 2D with 4 iterations. PET images were evaluated with count, SNR, FWHM from ROI drawn in the target region for quantitative tumor analysis. The size of molecular sieve motion target was $1.59{\times}2.50mm$. The reference motion target FWHM of vertical and horizontal was 2.91 mm and 1.43 mm, respectively. The vertical FWHM of static, 4 bin and 8 bin was 3.90 mm, 3.74 mm, and 3.16 mm, respectively. The horizontal FWHM of static, 4 bin and 8 bin was 2.21 mm, 2.06 mm, and 1.60 mm, respectively. Count of static, 4 bin, 8 bin, 12 bin and 16 bin was 4.10, 4.83, 5.59, 5.38, and 5.31, respectively. The SNR of static, 4 bin, 8 bin, 12 bin and 16 bin was 4.18, 4.05, 4.22, 3.89, and 3.58, respectively. The FWHM were improved in accordance with gate number increase. The count and SNR were not proportionately improve with gate number, but shown the highest value in specific bin number. We measured the optimal gate number what minimize the SNR loss and gain improved count when imaging lung tumor in small animal. The internal motion estimation provide localized tumor image and will be a useful method for organ motion prediction modeling without external motion monitoring system.

Development of a Small Animal Positron Emission Tomography Using Dual-layer Phoswich Detector and Position Sensitive Photomultiplier Tube: Preliminary Results (두층 섬광결정과 위치민감형광전자증배관을 이용한 소동물 양전자방출단층촬영기 개발: 기초실험 결과)

  • Jeong, Myung-Hwan;Choi, Yong;Chung, Yong-Hyun;Song, Tae-Yong;Jung, Jin-Ho;Hong, Key-Jo;Min, Byung-Jun;Choe, Yearn-Seong;Lee, Kyung-Han;Kim, Byung-Tae
    • The Korean Journal of Nuclear Medicine
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    • v.38 no.5
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    • pp.338-343
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    • 2004
  • Purpose: The purpose of this study was to develop a small animal PET using dual layer phoswich detector to minimize parallax error that degrades spatial resolution at the outer part of field-of-view (FOV). Materials and Methods: A simulation tool GATE (Geant4 Application for Tomographic Emission) was used to derive optimal parameters of small PET, and PET was developed employing the parameters. Lutetium Oxyorthosilicate (LSO) and Lutetium-Yttrium Aluminate-Perovskite(LuYAP) was used to construct dual layer phoswitch crystal. $8{\times}8$ arrays of LSO and LuYAP pixels, $2mm{\times}2mm{\times}8mm$ in size, were coupled to a 64-channel position sensitive photomultiplier tube. The system consisted of 16 detector modules arranged to one ring configuration (ring inner diameter 10 cm, FOV of 8 cm). The data from phoswich detector modules were fed into an ADC board in the data acquisition and preprocessing PC via sockets, decoder block, FPGA board, and bus board. These were linked to the master PC that stored the events data on hard disk. Results: In a preliminary test of the system, reconstructed images were obtained by using a pair of detectors and sensitivity and spatial resolution were measured. Spatial resolution was 2.3 mm FWHM and sensitivity was 10.9 $cps/{\mu}Ci$ at the center of FOV. Conclusion: The radioactivity distribution patterns were accurately represented in sinograms and images obtained by PET with a pair of detectors. These preliminary results indicate that it is promising to develop a high performance small animal PET.

Study on the Design Ideas and Planning Method of the Gameunsa Temple Architecture in Silla (신라감은사건축의 계획이념과 설계기술 고찰)

  • Lee, Jeongmin
    • Korean Journal of Heritage: History & Science
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    • v.54 no.1
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    • pp.238-259
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    • 2021
  • Gameunsa Temple is a Buddhist temple from the mid-Silla period. Construction began during the reign of King Munmu and was completed during the second year of King Sinmun's reign (682). This study is based on the results of excavations at the Gameunsa Temple site, exploring the findings presented in the literature in the field of history. This study also investigates the characteristics of the construction plan of Gameunsa Temple and its correlation with the political, social, and religious environment of the time. The results of the study are as follows: (1) First, it is confirmed that all of the buildings in the central block of Gameunsa Temple, such as the pagoda and corridor, the central gate, and the auditorium, fit within 216 cheoks by 216 cheoks (Goguryeo unit of measurement, estimated dimensions 353.30 mm), in terms of the base structure. This fact is highly significant considering the intent of the King in the mid-Silla period to advocate Confucian political ideals at the Donghaegu sites (Daewangam, Igyeondae Pavilion, and Gameunsa Temple), as confirmed by the relationship between the 'Manpasikjeok legend' and the Confucianism of the etiquette and the music; the relationship between the name of the 'Igyeondae Pavilion' and the 'I Ching'; and the relationship between the 'Taegeuk stones excavated from the Gameunsa Temple site' and the 'I Ching.' Additionally, it may be presumed that the number in the "Qian 216" on the Xici shang of 'I Ching' was used as a basis for determining the size of the central block in the early stages of the design of Gameunsa Temple. The layout of the halls and pagodas of Gameunsa Temple was planned to be within a 216-cheok-by-216-cheok area, from the edge to the center, i.e., on the central axis of the temple, in the following order: the central gate and auditorium, the north-south position of Geumdang Hall, the south corridor, the east-west buildings of the auditorium and the winged corridor, the east-west corridor, and the central position of the east-west stone pagoda. (2) Second, the coexistence of Confucianism and Buddhism in the architecture of Gameunsa Temple is based on the understanding of the Golden Light Sutra, originating from the aspirations of King Munmu to obtain the immeasurable merits (陰陽調和時不越序 日月星宿不失常度 風雨隨時無諸災横) and the light of the Buddha, which is metaphorically represented by the sun and the moon illuminating the whole world of Silla, a new nation with a Confucian political ideology, for a long time by "circumambulating the Buddha (旋繞)". It is also presumed that Gyeongheung, who was appointed by King Munmu to be the Guksa in his will and appointed as the Gukro after the enthronement of King Sinmun, was deeply involved in the conception and realization of the syncretism of Confucianism and Buddhism.