• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 하계학술대회 논문집
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• pp.347-350
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• 2001

A typical Mold method is to form a gate electrode, a gate oxide, and emitter tip after fabrication of mold shape using wet-etching of Si substrate. In this study, however, new Mold method using a side wall space structure is used in order to make sharper emitter tip with a gate electrode. Using LPCVD(low pressure chemical vapor deposition), a gate oxide and electrode layer are formed on a Si substrate, and then BPSG(Boro phospher silicate glass) thin film is deposited. After, the BPSG thin film is flowed into a mold as high temperature in order to form a sharp mold structure. Next TiN thin film is deposited as a emitter tip substance. The unfinished device with a glass substrate is bonded by anodic bonding techniques to transfer the emitters to a glass substrate, and Si substrate is etched using KOH-deionized water solution. Finally, we made sharp field emitter array with gate electrode on the glass substrate.

• 한국표면공학회:학술대회논문집
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• 한국표면공학회 1999년도 추계학술발표회 초록집
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• pp.56-56
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• 1999

For advanced TFT-LCD manufacturing processes, dry etching of thin-film layers(a-Si, $SiN_x$, SID & gate electrodes, ITO etc.) is increasingly preferred instead of conventional wet etching processes. To dry etch Al gate electrode which is advantageous for reducing propagation delay time of scan signals, high etch rate, slope angle control, and etch uniformity are required. For the Al gate electrode, some metals such as Ti and Nd are added in Al to prevent hillocks during post-annealing processes in addition to gaining low-resistivity($<10u{\Omega}{\cdot}cm$), high performance to heat tolerance and corrosion tolerance of Al thin films. In the case of AI-Nd alloy films, however, low etch rate and poor selectivity over photoresist are remained as a problem. In this study, to enhance the etch rates together with etch uniformity of AI-Nd alloys, magnetized inductively coupled plasma(MICP) have been used instead of conventional ICP and the effects of various magnets and processes conditions have been studied. MICP was consisted of fourteen pairs of permanent magnets arranged along the inside of chamber wall and also a Helmholtz type axial electromagnets was located outside the chamber. Gas combinations of $Cl_2,{\;}BCl_3$, and HBr were used with pressures between 5mTorr and 30mTorr, rf-bias voltages from -50Vto -200V, and inductive powers from 400W to 800W. In the case of $Cl_2/BCl_3$ plasma chemistry, the etch rate of AI-Nd films and etch selectivity over photoresist increased with $BCl_3$ rich etch chemistries for both with and without the magnets. The highest etch rate of $1,000{\AA}/min$, however, could be obtained with the magnets(both the multi-dipole magnets and the electromagnets). Under an optimized electromagnetic strength, etch uniformity of less than 5% also could be obtained under the above conditions.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2002년도 International Meeting on Information Display
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• pp.519-522
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• 2002

In this paper, we analyze the impact of plasma etching process induced device degradation on low temperature poly-Si TFTs. The results indicate the relationship between device degradation and PPID effect during plasma fabrication. The dual-gate structure, which is used to suppress leakage current, is also discussed in this research.

• 한국정보통신학회논문지
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• 제24권2호
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• pp.321-324
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• 2020

In this work, we developed a selective etching process for GaN that is a key process in p-GaN/AlGaN/GaN enhancement-mode (E-mode) power switching field-effect transistor (FET) fabrication. In order to achieve a high current density of p-GaN/AlGaN/GaN E-mode FET, the p-GaN layer beside the gate region must be selectively etched whereas the underneath AlGaN layer should be maintained. A selective etching process was implemented by oxidizing the surface of the AlGaN layer and the GaN layer by adding O2 gas to Cl2/N2 gas which is generally used for GaN etching. A selective etching process was optimized using Cl2/N2/O2 gas mixture and a high selectivity of 53:1 (= GaN/AlGaN) was achieved.

• EDISON SW 활용 경진대회 논문집
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• 제5회(2016년)
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• pp.365-367
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• 2016

나노와이어 FET은 natural length가 작아 단채널 효과가 MOSFET에 비해 줄어든다는 장점이 있어 미래의 소자 구조로 주목 받고 있다. 그런데 나노와이어 FET을 공정할 때 채널 etching에서 채널이 완벽하게 원형 구조를 가지는 것이 어렵다. 본 논문에서는 gate-all-around 실리콘 나노와이어 FET의 aspect ratio에 따른 트랜지스터의 특성 변화를 알아 보았다. 시뮬레이션 결과, aspect ratio가 작을수록 나노와이어 FET에서의 단채널 효과가 줄어드는 경향을 보였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2000년도 춘계학술대회 논문집 디스플레이 광소자 분야
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• pp.187-190
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• 2000

We fabricated general photo diode, surface etched photo diode and floating gate MOSFET by CMOS process. In a design stage, we expect that surface etched photo diode will be improved as to photo sensitivity. However, because the surface of silicon was damaged in etching process, the surface etched diode had a high dark current as well as low photo current level. Finally, we examined the current-voltage properties for the floating gate MOSFET on n-well and confirmed that the device can be act as an efficient photo-sensor. The floating gate MOSFET was operated in parasitic bipolar transistor mode.

• 한국광학회:학술대회논문집
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• 한국광학회 1991년도 제6회 파동 및 레이저 학술발표회 Prodeedings of 6th Conference on Waves and Lasers
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• pp.190-193
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• 1991

The monolithically integrated receiver OEIC using InGaAs/InP PIN PD, junction FET's and bias resistor has been fabricated on semi-insulating InP substrate. The fabrication process is highly compatible between PD and self-aligned JFET, and reduction in gate length is achieved using an anisotropic selective etching and a non-planar OMVPE process. The PIN photodetector with a 80 ${\mu}{\textrm}{m}$ diameter exhibits current of less than 5 nA and a capacitance of about 0.35 pF at -5 V bias voltage. An extrinsic transconductance and a gate-source capacitance of the JFET with 4 ${\mu}{\textrm}{m}$ gate length (gate width = 150 ${\mu}{\textrm}{m}$) are typically 45 mS/mm and 0.67 pF at 0 V, respectively. A voltage gain of the pre-amplifier is 5.5.

• 한국전기전자재료학회논문지
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• 제16권10호
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• pp.853-858
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• 2003

In this study, a new simplified technology for fabricating high density trench gate DMOSFETs using only three mask layers and TEOS/nitride spacer is proposed. Due to the reduced masking steps and self-aligned process, this technique can afford to fabricate DMOSFETs with high cell density up to 100 Mcell/inch$^2$ and cost-effective production. The resulting unit cell pitch was 2.3∼2.4${\mu}$m. The fabricated device exhibited a excellent specific on-resistance characteristic of 0.36m$\Omega$. cm$^2$ with a breakdown voltage of 42V. Moreover, time to breakdown of gate oxide was remarkably increased by the hydrogen annealing after trench etching.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2009년도 9th International Meeting on Information Display
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• pp.917-919
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• 2009

Effects of nano-silver contents(15~50wt%) on screen printed-etched gate electrodes and electrical characteristics of OTFTs were investigated. As Ag contents increased, the screen-printed film was transferred exactly without spreading and obtained the densely-packed layer with a stable and excellent conductivity but, its thickness was increased and surface became rougher. It was found that the leakage current of MIM devices and off-state currents of OTFTs became larger due to poor step coverage of PVP dielectric layer on the thick and rough gate electrodes for nano-Ag inks with Ag contents more than 30wt%.

• 대한전자공학회논문지
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• 제24권5호
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• pp.804-812
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• 1987

1\ulcorner gate MESFETs are fabricated on MOCVD and VPE grown GaAs wafers using photolithography, chemical wet etching and lift-off techniques. DC characteristics such as Vt, Gm, Rs, etc. are studied and active channel parameters of MESFET(a, n, Leff, \ulcorner)are analyzed for 1-4 \ulcorner gate FETs and 100\ulcorner FAT FET. The correlation between DC data and active channel parameters are experimentally analyzed. The measured transconductance and low-field mobility in the active channel for the 1\ulcorner gate MESFET made on MOCVD wafer are 67mS/mm and 2980cm\ulcornerVs respectively.