• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.146-146
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• 2010

Electrical properties of Large-grain-size TIT with 7/7 ${\mu}m$ channel width and length which gate insulator is made of 20nm $SiO_2$ and 80nm $SiN_x$. was fabricated and measured with Large-grain-size technic(MICC) and compared to ELA technic's data. The field-effect mobility was decreased from 106.78 to $88.74\;cm^2$/Vs and threshold voltage also decreased from -1.8382 to -0.9529 V, when TFT process is changed from ELA technic to MICC technic. Subthreshold swing, also, increased from 0.22 to 0.32 V/dec and $I_{on/off}$ ratio decreased from $1.12{\times}10^8$ to $5.75{\times}10^7$.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.21 no.9
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• pp.1139-1148
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• 1997

Compression waves propagating in a high-speed railway tunnel develops large pressure fluctuations on the train body or tunnel structures. The pressure fluctuations would cause an ear discomfort for the passengers and increase the aerodynamic resistance of trains. As a fundamental research to resolve the pressure wave phenomenon in the tunnel, experiments were carried out by using a shock tube with an open end. A blockage to model trains inside the tunnel was installed on the lower wall of shock tube, thus forming a sudden cross-sectional area reduction. The compression waves were obtained by the fast opening gate valve instead of a conventional diaphragm of shock tube and measured by the flush mounted pressure transducers with a high sensitivity. The experimental results were compared with the previous theoretical analyses. The results show that the ratio of the reflected to the incident compression wave at the sudden cross-sectional area reduction increases but the ratio of the passing to the incident compression wave decreases, as the incident compression wave becomes stronger. This experimental results are in good agreements with the previous theoretical ones. The maximum pressure gradient of the compression wave abruptly increases but the width of the wave front does not vary, as it passes over the sudden cross-sectional area reduction.

• Proceedings of the KIEE Conference
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• 1997.11a
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• pp.500-504
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• 1997

Current source inverter drives of auto sequentially commutated type are very popular in high power applications, because of simple power circuit configuration with four quadrant operation. But the six-step current output create harmonic problems and the input power factor of such a drive is not always good. In this respect pulse width modulated drives using gate turn off thyristors ( GTO ) are finding application, especially in traction drives. However the switching and snubber loses of a GTO do not permit the inverter switching frequency go beyond a few hundred hertz.This will again introduce low frequency harmonic problems. Multi level inverters of the 3-level and 5-level can be considered as an alternative to overcome the low switching frequency harmonic problem of the 2-level GTO inverters. But with multi level inverters the complexity of the power circuit increases. In this paper a combination of multi level ( 2-level and 3-level ) inverters and multi phase induction motor ( 3-phase and 6-phase) configurations are presented for high power VSI drives for traction applications with reduced inverter switching frequency requirements coupled with reduced voltage rating for the power switch.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.287-287
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• 2010

We report a new direct patterning method, called liquid bridge-mediated nanotransfer molding (LB-nTM), for the formation of two- or three-dimensional structures with feature sizes between tens of nanometers and tens of micron over large areas. LB-nTM is based on the direct transfer of various materials from a mold to a substrate via a liquid bridge between them. This procedure can be adopted for automated direct printing machines that generate patterns of functional materials with a wide range of feature sizes on diverse substrates. Arrays of TIPS-PEN TFTs were fabricated on 4" polyethersulfone (PES) substrates by LB-nTM using PDMS molds. An inverted staggered structure was employed in the TFT device fabrication. A 150 nm-thick indium-tin oxide (ITO) gate electrode and a 200 nm-thick SiO2dielectric layer were formed on a PES substrate by sputter deposition. An array of TIPS-PEN patterns (thickness: 60 nm) as active channel layers was fabricated on the substrate by LB-nTM. The nominal channel length of the TIPS-PEN TFT was 10 mm, while the channel width was 135 mm. Finally, the source and drain electrodes of 200 nm-thick Ag were defined on the substrate by LB-nTM. The TIPS-PEN TFTs can endure strenuous bending and are also transparent in the visible range, and therefore potentially useful for flexible and invisible electronics.

• Transactions on Electrical and Electronic Materials
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• v.16 no.4
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• pp.183-186
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• 2015

This research investigates the impact of charge spreading on the data retention of three-dimensional (3D) silicon-oxide-nitride-oxide-silicon (SONOS) flash memory where the charge trapping layer is shared along the cell string. In order to do so, this study conducts an electrical analysis of the planar SONOS test pattern where the silicon nitride charge storage layer is not isolated but extends beyond the gate electrode. Experimental results from the test pattern show larger retention loss in the devices with extended storage layers compared to isolated devices. This retention degradation is thought to be the result of an additional charge spreading through the extended silicon nitride layer along the width of the memory cell, which should be improved for the successful 3-D application of SONOS flash devices.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.3
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• pp.107-116
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• 1996

Recently, the flash memory has been abstracting great attention in the semiconductor market in the world because of its potential applications as mass storage devices. One of the most significant barriers to the scalling-down of the stacked-gate devices such as EPROM's and flash EEPROM's is the large subthreshold leakage in the unselected cells connected with the bit line of a selected cell in the array during programming. The large subthreshold leakge is majorly due to the capacitive coupling between the floating gates of the unselectd cells and the bit line of selected cell. In this paper, a new programming method to redcue significantly the drain turn-on leakage in the unselected cells during programming has been studied, where a little positive voltage (0.25-0.75V) is applied to the soruce during programming unlike the conventional programming method in which the source is grounded. The resutls of the PISCES simulations and the electrical measurements for the standard EPROM with 0.35.mu.m effective channel length and 1.0.mu.m effective channel width show that the subthreshold leakage in the unselectd cells is significantly large when the source is grounded, whereas it is negligibly small when the source is biased ot a little positive voltage during programming. On the other hadn, the positive bias on the source is found to have little effects on the programming speed of the EPROM.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.12
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• pp.1017-1021
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• 2007

To implement tera bit level non-volatile memories of low power and fast operation, proving statistical reproductivity and satisfying reliabilities at the nano-scale are a key challenge. We fabricate the charge trapping nano scaled SONOS unit memories and 64 bit flash arrays and evaluate reliability and performance of them. In case of the dielectric stack thickness of 4.5 /9.3 /6.5 nm with the channel width and length of 34 nm and 31nm respectively, the device has about 3.5 V threshold voltage shift with write voltage of $10\;{\mu}s$, 15 V and erase voltage of 10 ms, -15 V. And retention and endurance characteristics are above 10 years and $10^5$ cycle, respectively. The device with LDD(Lightly Doped Drain) process shows reduction of short channel effect and GIDL(Gate Induced Drain Leakage) current. Moreover we investigate three different types of flash memory arrays.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.24 no.5
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• pp.725-732
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• 2000

Laser induced incandescence (LII) method is frequently used to measure soot volume fraction in flames. In this study, experiments were performed to measure soot volume fraction in coaxial diffusion flame using LII method and calibrated with laser scattering/extinction method. The effects of laser intensity (>$1{\times}10^8W/cm^2$), laser wavelength (532nm, 1064nm) and detection wavelength (400nm, 600nm) on the LII signal were investigated. On the range of $4{\times}10^8{\sim}8{\times}10^8W/cm^2$ there were no effects of laser intensity on LII signal. Except these ranges, LII signal was increased with laser intensity. For the long gate width, the LII signals of the higher laser intensity (>${\vartheta}(GW/cm^2)$) cases had better correlation with soot volume fraction which were measured by laser extinction method compared with lower laser intensity cases. The errors of 2-dimensional cases at the calibration height were approximately 50% regardless of laser wavelength.

• Proceedings of the KIEE Conference
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• 1993.07b
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• pp.1289-1291
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• 1993

The hydrogenation effects on characteristics of polycrystalline silicon thin film transistors(poly-Si TFT's) of which the channel length varies from $2.5{\mu}m\;to\;20{\mu}m$ and poly-Si layer thickness is 50, 100, and 150 nm was investigated. After 1 hr hydrogenation annealing by PECVD, the threshold voltage shift decreased dependent on the channel length, but channel width may not alter the threshold voltage shift. In addition to channel length, the active poly-Si layer thickness may be an important parameter on hydrogenation effects, while gate poly-Si thickness may do not influence on the characteristics of TFT's. Considering our experimental results, we propose that channel length and active poly-Si layer thickness may be a key parameters of hydrogenation of poly-Si TFT's.

• Journal of Power Electronics
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• v.12 no.6
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• pp.886-894
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• 2012

This paper presents a secondary-side, dual-mode feedback LLC resonant controller IC with dynamic PWM dimming for LED backlight units. In order to reduce the cost, master and slave outputs can be generated simultaneously with a single LLC resonant core based on dual-mode feedback topologies. Pulse Frequency Modulation (PFM) and Pulse Width Modulation (PWM) schemes are used for the master stage and slave stage, respectively. In order to guarantee the correct dual feedback operation, Phased-Locked Loop (PLL)-based automatic duty control circuit is proposed in this paper. The chip is fabricated using $0.35{\mu}m$ Bipolar-CMOS-DMOS (BCD) technology, and the die size is $2.5mm{\times}2.5mm$. The frequency of the gate driver (GDA/GDB) in the clock generator ranges from 50 to 425 kHz. The current consumption of the LLC resonant controller IC is 40 mA for a 100 kHz operation frequency using a 15 V supply. The duty ratio of the slave stage can be controlled from 40% to 60% independent of the frequency of the master stage.