• Journal of The Korean Society of Agricultural Engineers
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• v.46 no.1
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• pp.27-34
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• 2004

A model test is carried out to investigate flow-induced vibration of a Tainter gate in estuary sulices. The gate model scaled with the ratio of 1：25 is made of acryl panel dimensioned 0.66m in width, 0.5m in height in the concrete test flume. Firstly, natural frequencies of the model gate are measured and the results are compared with the numerical results in order to verify the model. The amplitudes of the vibration are measured under the different gate opening and water level conditions in flow from the gate outside to the gate inside. Also 5 revised gate models with bottom width increased 0.5 cm each are tested under the different gate opening and water level. The results are analyzed to study the characteristics of the gate vibration. These test results are assessed in comparison with formerly test results, as a result, presents a design method of Tainter gate to reduce the gate vibration and a basic data for the guide manuals of gate management.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.344-345
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• 2012

The Gate-Induced-Drain-Leakage (GIDL) current with channel doping and width dependence are characterized. The GIDL currents are found to increase in MOSFETs with higher channel doping levels and the observed GIDL current is generated by the band-to-band-tunneling (BTBT) of electron through the reverse-biased channel-to-drain p-n junction. A BTBT model is used to fit the measured GIDL currents under different channel-doping levels. Good agreement is obtained between the modeled results and experimental data. The increase of the GIDL current at narrower widths in mainly caused by the stronger gate field at the edge of the shallow trench isolation (STI). As channel width decreases, a larger portion of the GIDL current is generated at the channel-isolation edge. Therefore, the stronger gate field at the channel-isolation edge causes the total unit-width GIDL current to increases for narrow-width devices.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.749-752
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• 2014

The device performance of n-channel MuGFET with different fin width, existence of spacer and channel length has been characterized. Tri-Gate structure(fin number=10) has been used. There are four kinds of Tri-Gate with fin width=55nm with spacer, fin width=70nm with spacer, fin width=55nm without spacer, fin width=70nm without spacer. DIBL, subthreshold swing, Vt roll-off, (above Short Channel Effect)and hot carrier stress degradation have been measured. From the experiment results, short Channel Effect with spacer was decreased, hot carrier degradation with spacer and narrow fin width was decreased. Therefore, layout of LDD structure with spacer and narrow fin width is desirable in short channel effect and hot carrier degradation.

• Journal of IKEEE
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• v.25 no.2
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• pp.350-355
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• 2021

IGBT is a power semiconductor device that contains both MOSFET and BJT structures, and it has fast switching speed of MOSFET, high breakdown voltage and high current of BJT characteristics. IGBT is a device that targets the requirements of an ideal power semiconductor device with high breakdown voltage, low V_CE-SAT, fast switching speed and high reliability. In this paper, we analyzed Gate oxide thickness, Trench Gate Width, and P+Emitter width, which are the top process parameters of 1,200V Trench Gate Field Stop IGBT, and suggested the optimized top process parameters. Using the Synopsys T-CAD Simulator, we designed IGBT devices with electrical characteristics that has breakdown voltage of 1,470 V, V_CE-SAT 2.17 V, Eon 0.361 mJ and Eoff 1.152 mJ.

• Journal of The Korean Society of Agricultural Engineers
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• v.46 no.2
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• pp.41-47
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• 2004

A model test is carried out to investigate flow-induced vibration of a Tainter gate in estuary sulices. The gate model scaled with the ratio of 1:25 is made of acryl panel dimensioned 0.66 m in width, 0.5 m in height in the concrete test flume. Firstly, natural frequencies of the model gate are measured and the results are compared with the numerical results in order to verify the model. In the flow from the gate inside to the gate outside, the amplitudes of the vibration are measured under the different gate opening and downstream water level conditions. Also revised gate models with 20 mm bottom width are tested under the different gate openings and water levels. The results are analyzed to study the characteristics of the Tainter gate vibration in the sea ward flow. These test results are assessed in comparison with the results in the lake ward flow, as a result, presents the dynamic characteristics of the Tainter gate and a basic data for the guide manuals of gate management.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.319-319
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• 2012

현재 폭넓게 이용되고 있는 STI (Shallow Trench Isolation) 공정에서 active edge 부분에 발생하는 기생 transistor의 subthreshold hump 특성을 제어하는 연구가 활발히 이루어지고 있다. 일반적으로 STI 공정을 이용하는 MOSFET에서 active edge 부분의 얇게 형성된 gate oxide, sharp한 active edge 형성, STI gap-fill 공정 중에 생기는 channel dopant out-diffusion은 subthreshold hump 특성의 주된 요인이다. 이와 같은 문제점을 해결하기 위해 active edge rounding process와 channel dopant compensation의 implantation을 이용하여 subthresold hump 특성 개선을 연구하였다. 본 연구는 STI 공정에 필요한 wafer와 phosphorus를 함유한 wafer를 한 chamber 안에서 auto-doping하는 방법을 이용하여 subthresold hump 특성을 구현하였다. phosphorus를 함유한 wafer에서 빠져나온 phosphorus가 STI 공정중인 wafer로 침투하여, active edge 부분의 channel dopant인 boron 농도를 상대적으로 낮춰 active edge 부분의 가 감소하고 leakage current를 증가시킨다. transistor의 channel length, gate width이고, wafer#No가 클수록 phosphorous를 함유한 wafer까지의 거리는 가까워진다. wafer #01은 hump 특성이 없고, wafer#20은 에서 심한 subthreshold hump 특성을 보였다. channel length 고정, gate width를 ~으로 가변하여 width에 따른 영향을 실험하였다. active 부분에 대한 SCM image로 확인된 phosphorus에 의한 active edge 부분의 boron 농도 감소와 gate width vs curve에서 확인된 phosphorus에 의한 감소가 narrow width로 갈수록 커짐을 확인하였다.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.581-582
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• 2006

In this paper, we investigate three different types of multi-fingered layout nMOSFET devices with varying $W_f$(unit finger width) and $N_f$(number of finger). Using layout modification, we improve $f_T$(current gain cutoff frequency) value of 15GHz without scaling down, and moreover, we decrease $NF_{min}$(minimum noise figure) by 0.23dB at 5GHz. The RF noise can be reduced by increasing $f_T$, choosing proper finger width, and reducing the gate resistance. For the same total gate width using multi-fingered layout, the increase of finger width shows high $f_T$ due to the reduced parasitic capacitance. However, this does not result in low $NF_{min}$ since the gate resistance generating high thermal noise becomes larger under wider finger width. We can obtain good RF characteristics for MOSFETs by using a layout optimization technique.

• Proceedings of the IEEK Conference
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• 2000.07b
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• pp.1119-1122
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• 2000

This paper describes on RF circuit simulation technique, especially on a RF modeling and a model extraction of a LDMOS(Lateral Diffused MOS) that has gate-width (Wg) dependence. Small-signal model parameters of the LDMOSs with various gate-widths extracted from S-parameter data are applied to make the relation between the RF performances and gate-width. It is proved that a source inductance (Ls) was not applicable to scaling rules. These extracted small-signal model parameters are also utilized to remove extrinsic elements in an extraction of a large-signal model (using HP Root MOSFET Model). Therefore, we can omit an additional measurement to extract extrinsic elements. When the large-signal model with Ls having the above gate-width dependence is applied to a high-power LDMOS module, the simulated performances (Output power, etc.) are in a good agreement with experimental results. It is proved that our extracted model and RF circuit simulation have a good accuracy.

• Journal of electromagnetic engineering and science
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• v.13 no.2
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• pp.127-133
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• 2013

We examined the scaling effects of a number of gate_fingers (N) and gate_widths (w) on the high-frequency characteristics of $0.1-{\mu}m$ metamorphic high-electron-mobility transistors. Functional relationships of the extracted small-signal parameters with total gate widths ($w_t$) of different N were proposed. The cut-off frequency ($f_T$) showed an almost independent relationship with $w_t$; however, the maximum frequency of oscillation ($f_{max}$) exhibited a strong functional relationship of gate-resistance ($R_g$) influenced by both N and $w_t$. A greater $w_t$ produced a higher $f_{max}$; but, to maximize $f_{max}$ at a given $w_t$, to increase N was more efficient than to increase the single gate_width.

• Journal of architectural history
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• v.19 no.2
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• pp.117-132
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• 2010

The Great south gate of Seoul Castle, Sung-Rye-Mun, the east gate of Seoul Castle, Hung-In-Ji-Mun, the south gate of Hwa-Sung Castle, Pal-Dal-Mun and the north gate of Hwa-Sung Castle, Jang-An-Mun are typical significant castle gate of Chosun Dynasty. They have a lot in common with exterior. Additionally there are also something common in dimensions. At first, the arch dimensions of lower story is very similar and the columns of upper story are the regular intervals. Purpose of this study is to confirm similarities above mentioned were intended on purpose and if then what was the reason. The results of this study were described separately as follows. 1. The widths of the arches were based on each 16Cheok and 18Cheok. 2. The heights of the arches followed less strictly rule than the widths. 3. The widths of the arches, 16Cheok was same size as width of middle-size road (中路, Jung-Ro) inside the Castle town in Chosun Dynasty. 4. The widths of the arches, 16Cheok was the standard size of exit went through castle and then the standard size of road arrived at one's destination. 5. The widths of the arches had an effect on the intervals between the columns of the upper story. Finally we recognized that in Chos${\u{o}}$n Dynasty the widths of the gate arches in Seoul castle and Hwa-Sung castle had relevance to the city planning largely and widths of the gate arches had an effect on the intervals between the columns of the upper story partly.