• Title/Summary/Keyword: Gate Security

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Smartphone Color-Code based Gate Security Control

  • Han, Sukyoung;Lee, Minwoo;Mariappan, Vinayagam;Lee, Junghoon;Lee, Seungyoun;Lee, Juyoung;Kim, Jintae;Cha, Jaesang
    • International journal of advanced smart convergence
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    • v.5 no.3
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    • pp.66-71
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    • 2016
  • Smart building gate security control system using smartphone integrated with near field communication (NFC) has become part of daily life usage these days. The technology change in replacing RF NFC device using visible light communication technology based approach growing faster in recent days. This paper propose a design and development of gate security control system using color code based user authentication ID generation as part of an intelligent access control system to control automatic door open and close. In this approach gate security access control use the recent visible light communication technology trends to transfer the user specific authentication code to door access control system using color code on smartphone screen. Using a camera in the door access control system (ACS), color codes on smartphone screens are detected and matched to the database of authenticated user to open the door automatically in gate security system. We measure the visual light communication technology efficiency as a part of the research and the experiments have revealed that more than 95% users authenticated correctly at the suggested experiment environment on gate security control system.

A Study on Detecting Kernel Based Call Gate Abuse (커널 기반 Call gate 오용 탐지에 관한 연구)

  • You, Dong-Hoon;Kim, Min-soo;Kim, Dong-Kook;Noh, Bong-Nam
    • Proceedings of the Korea Information Processing Society Conference
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    • 2010.04a
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    • pp.778-781
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    • 2010
  • Call gate 오용으로 인한 커널 공격 취약점은 커널 보안 문제점 중 하나로서 시스템 관리자들을 위협하고 있다. 이로 인해 근본적으로 커널 공격을 방어할 수 있는 대책이 시급하나 아직까지 효과적으로 Call gate 오용을 탐지할 수 있는 방법은 알려진 바가 없다. 본 논문에서는 적재가능커널모듈(loadable kernel module)을 이용하여 Call gate 오용을 통한 커널 공격을 탐지할 수 있는 방법을 기술하고자 한다.

Factors Influencing RFID Application Performance in Container Terminal Gate (컨테이너터미널 게이트에서의 RFID 적용성과에 영향을 미치는 요인)

  • Go, Bo-Chan;Chang, Myung-Hee
    • Journal of Navigation and Port Research
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    • v.34 no.10
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    • pp.807-815
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    • 2010
  • This study analyzed the correlation between RFID acceptance intention and application, and as a result, extracted the technical stability, system quality and security of RFID as factors that affect the intention of receiving RFID in container terminal gate through preliminary research. This analysis was done on individuals engaged in container terminals which are in operation by adopting RFID in container terminal gate presently, and by distributing totally 255 copies of questionnaire survey, 248 copies were collected. As a result of statistical analysis of this study, the following conclusions were made: First, the technical stability of RFID acceptance in container terminal gate was not statistically significantly high. Second, the system quality and the security of RFID acceptance in container terminal gate were statistically significantly high. Finally, container terminal gate RFID technology acceptance intention was statistically significantly high in application performance.

New Parity-Preserving Reversible Logic Gate (새로운 패리티 보존형 가역 논리게이트)

  • Kim, Sung-Kyoung;Kim, Tae-Hyun;Han, Dong-Guk;Hong, Seok-Hie
    • Journal of the Institute of Electronics Engineers of Korea SC
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    • v.47 no.1
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    • pp.29-34
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    • 2010
  • This paper proposes a new parity-preserving reversible logic gate. It is a parity-preserving reversible logic gate, that is, the party of the outputs matches that of the inputs. In recent year, reversible logic gate has emerged as one of the important approaches for power optimization with its application in low CMOS design, quantum computing and nono-technology. We show that our proposed parity-preserving reversible logic gate is much better in terms of number of reversible logic gates, number of garbage-outputs and hardware complexity with compared ti the exiting counterpart.

The Extraction of Fingerprint Corepoint And Region Separation using Labeling for Gate Security (출입 보안을 위한 레이블링을 이용한 영역 분리 및 지문 중심점 추출)

  • Lee, Keon-Ik;Jeon, Young-Cheol;Kim, Kang
    • Journal of the Korea Society of Computer and Information
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    • v.13 no.6
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    • pp.243-251
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    • 2008
  • This study is to suggest the extraction algorithms of fingerprint corepoint and region separation using the labeling for gate security in order that it might be applied to the fingerprint recognition effectively. The gate security technology is entrance control, attendance management, computer security, electronic commerce authentication, information protection and so on. This study is to extract the directional image by dividing the original image in $128{\times}128$ size into the size of $4{\times}4$ pixel. This study is to separate the region of directional smoothing image extracted by each directional by using the labeling, and extract the block that appeared more than three sorts of change in different directions to the corepoint. This researcher is to increase the recognition rate and matching rate by extracting the corepoint through the separation of region by direction using the maximum direction and labeling, not search the zone of feasibility of corepoint or candidate region of corepoint used in the existing method. According to the result of experimenting with 300 fingerprints, the poincare index method is 94.05%, the proposed method is 97.11%.

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Fault Detection Architecture of the Field Multiplication Using Gaussian Normal Bases in GF(2n (가우시안 정규기저를 갖는 GF(2n)의 곱셈에 대한 오류 탐지)

  • Kim, Chang Han;Chang, Nam Su;Park, Young Ho
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.24 no.1
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    • pp.41-50
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    • 2014
  • In this paper, we proposed an error detection in Gaussian normal basis multiplier over $GF(2^n)$. It is shown that by using parity prediction, error detection can be very simply constructed in hardware. The hardware overheads are only one AND gate, n+1 XOR gates, and one 1-bit register in serial multipliers, and so n AND gates, 2n-1 XOR gates in parallel multipliers. This method are detect in odd number of bit fault in C = AB.

Second-Order G-equivariant Logic Gate for AND Gate and its Application to Secure AES Implementation (AND 게이트에 대한 2차 G-equivariant 로직 게이트 및 AES 구현에의 응용)

  • Baek, Yoo-Jin;Choi, Doo-Ho
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.24 no.1
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    • pp.221-227
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    • 2014
  • When implementing cryptographic algorithms in mobile devices like smart cards, the security against side-channel attacks should be considered. Side-channel attacks try to find critical information from the side-channel infromation obtained from the underlying cryptographic devices' execution. Especially, the power analysis attack uses the power consumption profile of the devices as the side-channel information. This paper proposes a new gate-level countermeasure against the power analysis attack and the glitch attack and suggests how to apply the measure to securely implement AES.

Development of field programmable gate array-based encryption module to mitigate man-in-the-middle attack for nuclear power plant data communication network

  • Elakrat, Mohamed Abdallah;Jung, Jae Cheon
    • Nuclear Engineering and Technology
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    • v.50 no.5
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    • pp.780-787
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    • 2018
  • This article presents a security module based on a field programmable gate array (FPGA) to mitigate man-in-the-middle cyber attacks. Nowadays, the FPGA is considered to be the state of the art in nuclear power plants I&C systems due to its flexibility, reconfigurability, and maintainability of the FPGA technology; it also provides acceptable solutions for embedded computing applications that require cybersecurity. The proposed FPGA-based security module is developed to mitigate information-gathering attacks, which can be made by gaining physical access to the network, e.g., a man-in-the-middle attack, using a cryptographic process to ensure data confidentiality and integrity and prevent injecting malware or malicious data into the critical digital assets of a nuclear power plant data communication system. A model-based system engineering approach is applied. System requirements analysis and enhanced function flow block diagrams are created and simulated using CORE9 to compare the performance of the current and developed systems. Hardware description language code for encryption and serial communication is developed using Vivado Design Suite 2017.2 as a programming tool to run the system synthesis and implementation for performance simulation and design verification. Simple windows are developed using Java for physical testing and communication between a personal computer and the FPGA.

A Study on the BIL Bitstream Reverse-Engineering Tool-Chain Analysis (BIL 비트스트림 역공학 도구 분석 연구)

  • Yoon, Junghwan;Seo, Yezee;Kim, Hoonkyu;Kwon, Taekyoung
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.28 no.2
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    • pp.287-293
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    • 2018
  • Field Programmable Gate Array (FPGA) is widely used in a variety of fields because of its ability to be programmed as desired. However, when an externally implemented program is loaded on FPGA in the form of a bitstream, there is a possibility that hardware Trojans which cause malfunctions or leak information may be included. For this reason, bitstream reverse engineering is essential, and therefore related research has been conducted, such as BIL. In this paper, we analyze the BIL bitstream reverse engineering tool, which is the most representative algorithm, regarding its performance and limitations.

Implementation of Lightweight Block Cipher for Ubiquitous Computing Security (유비쿼터스 컴퓨팅 보안을 위한 경량 블록 암호 구현)

  • Kim, Sung-Hwan;Kim, Dong-Seong;Song, Young-Deog;Park, Jong-Sou
    • Convergence Security Journal
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    • v.5 no.3
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    • pp.23-32
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    • 2005
  • This paper presents a 128-bit Reversible Cellular Automata (RCA) based lightweight block cipher for Ubiquitous computing security. To satisfy resource-constraints for Ubiquitous computing, it is designed as block architecture based on Cellular Automata with high pseudo-randomness. Our implementation requires 704 clock cycles and consumes 2,874 gates for encryption of a 128-bit data block. In conclusion, the processing time outperformed that of AES and NTRU by 31%, and the number of gate was saved by 20%. We evaluate robustness of our implementation against both Differential Cryptanalysis and Strict Avalanche Criterion.

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