• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.7
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• pp.1393-1398
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• 2009

Conventionally, etching is first considered for microelectronics fabrication process and is specially important in process of a-Si:H thin film transistor for LCD. In this paper, we stabilize properties of device by development of wet and dry etching process. The a-Si:H TFTs of this paper is inverted staggered type. The gate electrode is lower part. The gate electrode is formed by patterning with length of 8 ${\mu}$m${\sim}$16 ${\mu}$m and width of 80${\sim}$200 ${\mu}$m after depositing with gate electrode (Cr) 1500 ${\AA}$under coming 7059 glass substrate. We have fabricated a-SiN:H, conductor, etch-stopper and photo resistor on gate electrode in sequence, respectively. The thickness of these thin films is formed with a-SiN:H (2000 ${\mu}$m), a-Si:H(2000 ${\mu}$m) and n+a-Si:H (500 ${\mu}$m), We have deposited n-a-Si:H, NPR(Negative Photo Resister) layer after forming pattern of Cr gate electrode by etch-stopper pattern. The NPR layer by inverting pattern of upper gate electrode is patterned and the n+a-Si:H layer is etched by the NPR pattern. The NPR layer is removed. After Cr layer is deposited and patterned, the source-drain electrode is formed. In the fabricated TFT, the most frequent problems are over and under etching in etching process. We were able to improve properties of device by strict criterion on wet, dry etching and cleaning process.

• Design & Manufacturing
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• v.11 no.1
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• pp.14-18
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• 2017

Recently, the injection-molded products are lighter, and thinner than ever. In this work, Injection molding simulation was conducted to analysis the filling pattern imbalance in high speed injection molding process for thin-wall injection component, 8 inches LGP. Numerical analysis shows that shear heated polymer near the side wall causes filling imbalance between center and side of cavity. Short shot experiments were conducted and compared with simulation results. Filling imbalance ratio showed a tendency to increase for wider fan gate.

• Proceedings of the Korean Powder Metallurgy Institute Conference
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• 2006.09a
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• pp.505-506
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• 2006

This study is focused on the manufacturing technique of powder injection molding of watch case made from zirconia powder. A series of computer simulation processes were applied to the prediction of the flow pattern in the inside of the mould and defects as weld-line. The material properties of melted feedstock, including the PVT graph and thermal viscosity flowage properties were measured to obtain the input data to be used in a computer simulation. Also, a molding experiment was conducted and the results of the experiment showed a good agreement with the simulation results for flow pattern and weld line location. On the other hand, gravity and inertia effects have an influence on the velocity of the melt front because of the high density of ceramic powder particles during powder injection molding in comparison with polymer's injection molding process. In the experiment, the position of the melt front was compared with the upper gate and lower gate positions. The gravity and inertia effect could be confirmed in the experimental results.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.83-83
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• 2009

We studied about the effect of newly developed etchant for spacer etch process in gate patterning. With the 110nm CMOS technology, first, we changed the gate pattern size and investigated the variation of spacer etch profile according to the difference in gate length. Second, thickness of spacer nitride was changed and effect of etch ant on difference in nitride thickness was observed. In addition to these, spacer etch power was added as test item for variation of etch profile. We investigated the etch profiles with SEM and TEM analysis was used for plasma damage check. With these results we could check the process margins for gate patterning which could hold best performance and choose the condition for best spacer etch profile.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07b
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• pp.1119-1122
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• 2005

A selective deposition of Co thin films for thin film transistor gate electrode has been carried out by the growth with combination of micro-contact printing and metal organic chemical vapor deposition (MOCVD). This results in the elimination of optical lithography process. MOCVD has been employed to selectively deposit Co films on preformed OTS gate pattern by using micro-contact printing (${\mu}CP$). A hydrogenated amorphous silicon TFT with a Co gate selectively formed on SAMs patterned structure exhibited a subthreshold slope of 0.88V/dec, and mobility of $0.35cm^2/V-s$, on/off current ratio of $10^6$, and a threshold voltage of 2.5V, and thus demonstrating the successful application of the novel bottom-up approach into the fabrication of a-Si:H TFTs.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.3 no.1
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• pp.235-244
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• 1999

This Paper proposes a new compaction algorithm for IDDQ testing in CMOS Circuits. A primary test pattern is generated by the primitive fault pattern which is able to detect GOS(gate-oxide short) and the bridging faults in an internal primitive gate. The new algorithm can reduce the number of the test vectors by decreasing the don't care(X) in the primary test pattern. The controllability of random number is used on processing of the backtrace together four ones of heuristics. The simulation results for the ISCAS-85 benchmark circuits show that the test vector reduction is more than 45% for the large circuits on the average compared to static compaction algorithms.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.5
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• pp.601-608
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• 2014

In this paper, we have characterized the electrical properties related to gate leakage current in AlGaN/GaN MISHFETs with varying the thickness (0 to 10 nm) of $Al_2O_3$ gate insulator which also serves as a surface protection layer during high-temperature RTP. The sheet resistance of the unprotected TLM pattern after RTP was rapidly increased to $1323{\Omega}/{\square}$ from the value of $400{\Omega}/{\square}$ of the as-grown sample due to thermal damage during high temperature RTP. On the other hand, the sheet resistances of the TLM pattern protected with thin $Al_2O_3$ layer (when its thickness is larger than 5 nm) were slightly decreased after high-temperature RTP since the deposited $Al_2O_3$ layer effectively neutralizes the acceptor-like states on the surface of AlGaN layer which in turn increases the 2DEG density. AlGaN/GaN MISHFET with 8 nm-thick $Al_2O_3$ gate insulator exhibited extremely low gate leakage current of $10^{-9}A/mm$, which led to superior device performances such as a very low subthreshold swing (SS) of 80 mV/dec and high $I_{on}/I_{off}$ ratio of ${\sim}10^{10}$. The PF emission and FN tunneling models were used to characterize the gate leakage currents of the devices. The device with 5 nm-thick $Al_2O_3$ layer exhibited both PF emission and FN tunneling at relatively lower gate voltages compared to that with 8 nm-thick $Al_2O_3$ layer due to thinner $Al_2O_3$ layer, as expected. The device with 10 nm-thick $Al_2O_3$ layer, however, showed very high gate leakage current of $5.5{\times}10^{-4}A/mm$ due to poly-crystallization of the $Al_2O_3$ layer during the high-temperature RTP, which led to very poor performances.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.11b
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• pp.181-184
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• 2001

Chemical Mechanical Polishing(CMP) of Shallow Trench Isolation(STD structure in 0.18 m semiconductor device fabrication is studied. CMP process is applied for the STI structure with and without reverse moat pattern and End Point Detection (EPD) method is tested. To optimize the transistor properties related metal 1 parameters. we studied the correlation between CMP thickness of STI using high selectivity slurry. DOE of gate etch recipe, and 1st metal DC values. Remaining thickness of STI CMP is proportional to the thickness of gate-etch process and this can affect to gate profile. As CMP thickness increased. the N-poly foot is deteriorated. and the P-Poly Noth is getting better. If CD (Critical Dimension) value is fixed at some point,, all IDSN/P values are in inverse proportional to CMP thickness by reason of so called Profile Effect. Weve found out this phenomenon in all around DOE conditions of Gate etch process and we also could understand that it would not have any correlation effects between VT and CMP thickness in the range of POE 120 sec conditions. As CMP thickness increased by $100\AA$. 3.2 $u\AA$ of IDSN is getting better in base 1 condition. In POE 50% condition. 1.7 $u\AA$ is improved. and 0.7 $u\AA$ is improved in step 2 condition. Wed like to set the control target of CD (critical dimension) in gate etch process which can affect Idsat, VT property versus STI topology decided by CMP thickness. We also would like to decide optimized thickness target of STI CMP throughout property comparison between conventional STI CMP with reverse moat process and newly introduced STI CMP using high selectivity slurry. And we studied the process conditions to reduce Gate Profile Skew of which source known as STI topology by evaluation of gate etch recipe versus STI CMP thickness.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.11a
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• pp.181-184
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• 2001

Chemical Mechanical Polishing(CMP) of Shallow Trench Isolation(STI) structure in 0.18 m semiconductor device fabrication is studied. CMP process is applied for the STI structure with and without reverse moat pattern and End Point Detection (EPD) method is tested. To optimize the transistor properties related metal 1 parameters, we studied the correlation between CMP thickness of STI using high selectivity slurry, DOE of gate etch recipe, and 1st metal DC values. Remaining thickness of STI CMP is proportional to the thickness of gate-etch process and this can affect to gate profile. As CMP thickness increased, the N-poly foot is deteriorated, and the P-Poly Noth is getting better. If CD (Critical Dimension) value is fixed at some point, all IDSN/P values are in inverse proportional to CMP thickness by reason of so called Profile Effect. Weve found out this phenomenon in all around DOE conditions of Gate etch process and we also could understand that it would not have any correlation effects between VT and CMP thickness in the range of POE 120 sec conditions. As CMP thickness increased by 100 ${\AA}$, 3.2 u${\AA}$ of IDSN is getting better in base 1 condition. In POE 50% condition, 1.7 u${\AA}$ is improved, and 0.7 u${\AA}$ is improved in step 2 condition. Wed like to set the control target of CD (critical dimension) in gate etch process which can affect Idsat, VT property versus STI topology decided by CMP thickness. We also would like to decide optimized thickness target of STI CMP throughout property comparison between conventional STI CMP with reverse moat process and newly introduced STI CMP using high selectivity slurry. And we studied the process conditions to reduce Gate Profile Skew of which source known as STI topology by evaluation of gate etch recipe versus STI CMP thickness.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1065-1068
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• 1998

This paper proposes a new test generation method. Most of the test generation methods are gate-level based, but our scheme is VHDL based, especially in other word, behavioral-level based. Our test pattern generation method uses software test method. And we generate deterministic test pattern with this method. The purpose of our method is to reduce the time and effort to generate the test patterns for the end-product test of IC.