• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.111-117
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• 2006

Reconfigurable CMOS low-noise amplifier (LAN) has been developed for multi-mode/multi-band wireless receiver. By employing common-gate input stage, the performance can be optimized for multiple operation bands by simply controlling the output load impedance. Although the conventional common-gate LAN has larger than 3dB noise figure (NF), the newly developed negative feedback scheme enables the common-gate input LNA to have less than 2dB NF. To have optimum linearity performance of wireless receiver, the gain of the LNA can be controlled. The LNA implemented in a 0.13mm CMOS technology shows $19{\sim}20dB$ voltage gain, $1.7{\sim}2.0dB$ NF, -2dBm iIP3 at $1.8{\sim}2.5GHz$ frequency range. The LNA dissipates 7mW from a 1.2V supply voltage.

• Journal of Information Display
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• v.2 no.3
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• pp.66-71
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• 2001

MCFEDs (MOSFET-Contoolled Field Emission Displays) were fabricated to evaluate the validity of MCFEA for display application. The electrical properties of FEAs (Field Emitter Arrays), HVMOSFETs (High-Voltage MOSFETs), and MCFEAs (MOSFET-Controlled Field Emitter Arrays) were measured. The extraction gate voltage of the FEAs to obtain the anode current of 10 nA/tip was around 71 V. The breakdown voltages of the HVMOSFETs were above 81 V for all the samples. The I-V characteristics of the MCFEAs showed that the emission currents of the FEAs were well controlled depending on the control gate voltages of the HVMOSFETs. To avoid the harmful effects during the packaging process, the performance of the MCFEDs was evaluated in a high vacuum chamber. The emission images of the MCFEDs were controlled through very-through operation. From the comparison with a conventional FED, it was proven that the poor uniformity of FED could be improved through the integration with HVMOSFET.

• The Transactions of the Korean Institute of Power Electronics
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• v.24 no.6
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• pp.459-462
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• 2019

This work presents methods for reducing overshoot voltages across the drain-source of silicon carbide (SiC) MOSFETs in grid-connected hybrid active neutral-point-clamped (ANPC) inverters. Compared with 3-level NPC-type inverter, the hybrid ANPC inverter can realize the high efficiency. However, SiC MOSFETs conduct its switching operation at high frequencies, which cause high overshoot voltages in such devices. These overshoot voltages should be reduced because they may damage switching devices and result in electromagnetic interference (EMI). Two major strategies are used to reduce the overshoot voltages, namely, adjusting the gate resistor and using a snubber capacitor. In this paper, advantages and disadvantages of these methods will be discussed. The effectiveness of these strategies is verified by experimental results.

• ETRI Journal
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• v.39 no.4
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• pp.570-581
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• 2017

Multiplication in finite fields is used in many applications, especially in cryptography. It is a basic and the most computationally intensive operation from among all such operations. Several systolic multipliers are proposed in the literature that offer low hardware complexity or high speed. In this paper, a bit-parallel polynomial basis systolic multiplier for generic irreducible polynomials is proposed based on a modified interleaved multiplication method. The hardware complexity and delay of the proposed multiplier are estimated, and a comparison with the corresponding multipliers available in the literature is presented. Of the corresponding multipliers, the proposed multiplier achieves a reduction in the hardware complexity of up to 20% when compared to the best multiplier for m = 163. The synthesis results of application-specific integrated circuit and field-programmable gate array implementations of the proposed multiplier are also presented. From the synthesis results, it is inferred that the proposed multiplier achieves low power consumption and low area complexitywhen compared to the best of the corresponding multipliers.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.04a
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• pp.169-172
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• 2000

A-Si:H and poly-Si TFT characteristics were investigated using an inverted staggered type TFT. The poly-Si films were achieved by various anneal techniques ; isothermal, RTA, and excimer laser anneal. The TFT on as-grown a-Si:H exhibited a low field effect mobility, transconductance, and high gate threshold voltage. Some films were annealed at temperatures from $200^{\circ}C$ to $1000^{\circ}C$. The TFT on poly-Si showed an improved $I_{on}/I_{off}$ ratio of $10^6$, reduced gate threshold voltage, and increased field effect mobility by three orders. Inverter operation was examined to verify logic circuit application using the poly-Si TFTs.

• Design & Manufacturing
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• v.2 no.6
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• pp.49-55
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• 2008

Double-injection molding can inject two different materials or two colors in the same mold and process. If this injection process use, product has ability because the base part maintain strength and specified part can inject soft-material. It makes the cost down by single operation automatically for saving wages. In this paper, we designed double-injection mold for automobile remote control to inject secondary using this part as insert after inject external appearance of product. CAE analysis was progressed gate location and runner size as variable and analysis result is reflected in mold design process. As a result, it could solved badness that is generated at the conventional mold. Additionally, cost is downed by reducing loss of runner as well as could omit painting process because surface of finished product is improved through new mold.

• Transactions of Materials Processing
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• v.15 no.5 s.86
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• pp.347-353
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• 2006

The delivery system such as sprue, runner and gate is a waste of resin in injection molding operation. In this study the reduction of runner size has been investigated using injection molding CAE softwares, Moldflow and Moldex3D, and commercial CFD Softwares, Fluent and Polyflow. To verify the computational results experiment was performed. There were three considerations in deciding optimal runner size in this study: minimum pressure at the gate that makes resin fully filled in the cavity, minimum runner size that compensates shrinkage of resin in the cavity, and frozen layer thickness formed in the runner during injection. Through the computer simulations the optimal runner size that satisfies those three considerations has been decided. Although the computational results among the softwares were slightly different, it was enough to predict the optimal runner size. The previous runner diameter was 8 mm and predicted optimal size was 5 mm. This was verified by injection molding experiment. Thus, the way of CAE application in deciding optimal runner size adapted in this study would be appropriated.

• Journal of Power Electronics
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• v.7 no.4
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• pp.278-285
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• 2007

Recently, plasma display panels (PDP) have become the most promising candidate in the market for large screen size flat panel displays. PDPs have many merits such as a fast display response time and wide viewing angle. However, there are still concerns about high cost because they require complex driving circuits composed of high power switching devices to generate various voltage waveforms for three operational modes of reset, scan, and sustain. Conventional PDP driving circuits use path switches for voltage separation and a scan switch to offer a scan voltage for reset and scan operations, respectively. In addition, there exist reset switches to initialize PDPs by regulating the wall charge conditions with ramp shaped pulses, which means the necessity of specific power devices for the reset operation. Because power for the plasma discharge accompanied by a large current is transferred to a panel via path switches, high power rating switches are used for path switches. Therefore, this paper proposes a novel low-cost PDP driving scheme achieved by not only eliminating path switches but also merging the function of reset switches into other switches used for sustain or scan operations. The simulated voltage waveforms of the proposed topology and experimental results implemented in a 42-inch panel to demonstrate the validity of using a new gate driver that merges the functions of power switches are presented.

• Transactions on Electrical and Electronic Materials
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• v.14 no.3
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• pp.139-142
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• 2013

Silicon nanowire (SiNW) silicon-oxide-nitride-oxide-silicon (SONOS) flash memory devices were fabricated and their electrical characteristics were analyzed. Compared to planar SONOS devices, these SiNW SONOS devices have good program/erase (P/E) characteristics and a large threshold voltage ($V_T$) shift of 2.5 V in 1ms using a gate pulse of +14 V. The devices also show excellent immunity to short channel effects (SCEs) due to enhanced gate controllability, which becomes more apparent as the nanowire width decreases. This is attributed to the fully depleted mode operation as the nanowire becomes narrower. 3D TCAD simulations of both devices show that the electric field of the junction area is significantly reduced in the SiNW structure.

• Environmental Engineering Research
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• v.21 no.2
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• pp.171-179
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• 2016

This study analyzes guidelines to select optimum number of grids to represent behavior of a given water system appropriately. The EFDC model was chosen as a 3-D hydrodynamic and water quality model and salt was chosen as a surrogate variable of pollutant. The model is applied to an artificial canal that receives salt water from coastal area and fresh water from a river from respective gate according to previously developed gate operation rule. Grids are subdivided in vertical and horizontal (longitudinal) directions, respectively until no significant changes are found in salinity concentrations. The optimum grid size was determined by comparing errors in average salt concentrations between a test grid systems against the most complicated grid system. MSE (mean squared error) and MAE (mean absolute error) are used to compare errors. The CFL (Courant-Friedrichs-Lewy) number was used to determine the optimum number of grid systems for the study site though it can be used when explicit numerical method is applied only. This study suggests errors seem acceptable when both MSE and MAE are less than unity approximately.