• Journal of Korean Society of Coastal and Ocean Engineers
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• v.17 no.4
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• pp.269-279
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• 2005

Numerical simulations were done using depth integrated ADCIRC model in order to evaluate dynamic response on the inner Saemankeum reservoir due to flood flow and gate operation for the both situations of dike construction and inner development. According to 2-dimensional dynamic flood routing, temporal variation of hydrographs shows sensitive at upstream riverine region while it becomes stable from the center part of the reservoir due to sudden expansion of physical changes. Dynamic response of hydraulic changes such as water surface elevation and velocity on the inner region arises suddenly by gate operation and more rapidly after the inner development than dike construction. Temporal surface fluctuation arises during inflowging of outer sea water and propagates upstream up to 10km to 16km in accordance with inner development status.

• Journal of Korean Society of Coastal and Ocean Engineers
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• v.22 no.4
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• pp.258-271
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• 2010

In order to figure out hydrodynamic and water quality changes after completion of dike construction of the Saemangeum, which behaves as a semi-enclosed estuarine lake, numerical simulations based on fine grid structure by using EFDC were intensively carried out. In this study some limitations of precedent study has been improved and gate operation were considered. Also 3 phases such as air-water-sediment interaction modeling was considered. It is clear that inner mixing of the Saemangeum is dominated by Mankyeong and Dongjin riverine discharges rather than the gate opening influence through the Lagrangian particle tracking simulations. Vertical DO structure after the dike completion shows steep gradient especially at Dongjin river estuary due to lessen of outer sea water exchange. Increasing SOD at stagnantly changed man-made reservoir might cause oxygen deficiency and accelerating degradation of water quality. According to TSI evaluation test representing eutrophication status, it shows high possibility of eutrophication along Mankyeong waterway in spite of dike completion, while the index is getting high after final closing along Dongjin waterway. Numerical tests with gate operations show significant differences in water quality. Thus it should be noted that proper gate operation plays a major role in preserving target water quality and management for inner development plan.

• KSCE Journal of Civil and Environmental Engineering Research
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• v.30 no.3B
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• pp.277-284
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• 2010

To examine how the width of connecting channels, the width of the Kumho lock gate, and the opening/shutting criteria of the Yeongam connecting channel lock gate affect the flood stage of Lake Yeongsan, Lake Yeongam, and Lake Kumho, located in the lower reaches of the Yeongsan River, unsteady flood routing was performed by connecting the three lakes into a single interlinked system. The coupled operation of the three lakes was found to have little effect when the widths of the lock gates and the Yeongam and Kumho connecting channels are set at the current level. The most effective way to lower the water level in Lake Yeongsan was to widen the Yeongam connecting channel, but this caused the water level in Lake Yeongam to rise. To lower the increased water level in Lake Yeongam by utilizing the water storage capacity of Lake Kumho, it was necessary to widen both the Kumho lock gate and the Kumho connecting channel. It was found that the optimum opening/shutting criterion for the Yeongam connecting channel lock gate is approximately EL.(+)0.8 m under the simulated conditions used in this study and the criterion allows of maximal lowering of the water levels in Lake Yeongam and Lake Kumho while maintaining a near-constant water level in Lake Yeongsan.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1998.11a
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• pp.145-150
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• 1998

8$\times$8 bit scaled SONOSFET NAND type flash EEPROM that shows better characteristics on cell density and endurance than NOR type have been designed and its electrical characteristics are verified with computer aided simulation. For the simulation, the spice model parameter was extracted from the sealed down SONOSFET that was fabricated by $1.5mutextrm{m}$ topological design rule. To improve the endurance of the device, the EEPROM design to have modified Fowler-Nordheim tunneling through the whole channel area in Write/Erase operation. As a result, it operates Write/Erase operation at low current, and has been proven Its good endurance. The NAND type flash EEPROM, which has upper limit of V$_{th}$, has the upper limit of V$_{th}$ as 4.5V. It is better than that of floating gate as 4V. And a EEPROM using the SONOSFET without scaling (65$\AA$-l65$\AA$-35$\AA$), was also designed and its characteristics have been compared. It has more possibliity of error from the V$_{th}$ upper limit as 4V, and takes more time for Read operation due to low current. As a consequence, it is proven that scaled down SONOSFET is more pertinent than existing floating gate or SONOSFET without scaling for the NAND type flash EEPROM.EPROM.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.4
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• pp.300-304
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• 2008

A novel characterization method was investigated to estimate the trap generation during the program /erase cycles in nand flash memory cell. Utilizing Fowler-Nordheim tunneling current, floating gate potential and oxide electric field, we established a quantitative model which allows the knowledge of threshold voltage (Vth) as a function of either program or erase operation time. Based on our model, the derived results proved that interface trap density (Nit) term is only included in the program operation equation, while both Nit and oxide trap density (Not) term are included in the erase operation equation. The effectiveness of our model was tested using 50 nm nand flash memory cell with floating gate type. Nit and Not were extracted through the analysis of Program/Erase speed with respect to the endurance cycle. Trap generation and cycle numbers showed the power dependency. Finally, with the measurement of the experiment concerning the variation of cell Vth with respect to program/erase cycles, we obtained the novel quantitative model which shows similar results of relationship between experimental values and extracted ones.

• Journal of Power Electronics
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• v.18 no.1
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• pp.23-33
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• 2018

Silicon Carbide (SiC) MOSFET belongs to the family of wide-band gap devices with inherit property of low switching and conduction losses. The stable operation of SiC MOSFET at higher operating temperatures has invoked the interest of researchers in terms of its application to high power density (HPD) power converters. This paper presents a performance study of SiC MOSFET based two-phase interleaved boost converter (IBC) for regulation of avionics bus voltage in more electric aircraft (MEA). A 450W HPD, IBC has been developed for study, which delivers 28V output voltage when supplied by 24V battery. A gate driver design for SiC MOSFET is presented which ensures the operation of converter at 250kHz switching frequency, reduces the miller current and gate signal ringing. The peak current mode control (PCMC) has been employed for load voltage regulation. The efficiency of SiC MOSFET based IBC converter is compared against Si counterpart. Experimentally obtained efficiency results are presented to show that SiC MOSFET is the device of choice under a heavy load and high switching frequency operation.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.8
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• pp.1-9
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• 1999

Timing-level circuit analyses are used to obtain fast and accurate results, and the analysis of gate and interconnect delay is necessary to validate the correctness of circuit design. This paper proposes an efficient algorithm which simultaneously calculates the gate delay and the transition time of linearized voltage source for subsequent interconnect delay calculation. The notion of effective capacitance is used to calculate the gate delay and the transition time of linearized voltage source which considers the on-resistance of driving gate. The procedure for obtaining the gate delay and the transition time of linearized voltage source has been developed through an iterative operation using the precharacterized data of gates. While previous methods require extra information for the transition time calculation of linearized voltage sources, our method uses the derived data during the gate delay calculation process, which does not require any change in the precharacterization process.

• The Journal of the Korea institute of electronic communication sciences
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• v.12 no.1
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• pp.189-194
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• 2017

The reversibility of a quantum logic circuit can be realized when two reversible conditions of information reversible and energy reversible circuits are satisfied. In this paper, we have modeled the computation cycle required to recover the information reversibility from the multivalued quantum logic to the original state. For modeling, we used a function embedding method that uses a unitary switch as an arithmetic exponentiation switch. In the quantum logic circuit, if the adjoint gate pair is symmetric, the unitary switch function shows the balance function characteristic, and it takes 1 cycle operation to recover the original information reversibility. Conversely, if it is an asymmetric structure, it takes two cycle operations by the constant function. In this paper, we show that the problem of 2-cycle restoration according to the asymmetric structure when the hybrid MCT gate is realized with the ternary M-S gate can be solved by equivalent conversion of the asymmetric gate to the gate of the symmetric structure.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.10
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• pp.1-6
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• 2008

The holding voltage of the high-voltage MOSFETs in snapback condition is much smaller than the power supply voltage. Such characteristics may cause the latcup-like problems in the Smart Power ICs if these devices are directly used in the ESD (Electrostatic Discharge) power clamp. In this work, a latchup-free design based on the Drain-Extended PMOS (DEPMOS) adopting gate VDD structure is proposed. The operation region of the proposed gate-VDD DEPMOS ESD power clamp is below the onset of the snapback to avoid the danger of latch-up. From the measurement on the devices fabricated using a $0.35\;{\mu}m$ BCD (Bipolar-CMOS-DMOS) Process (60V), it was observed that the proposed ESD power clamp can provide 500% higher ESD robustness per silicon area as compared to the conventional clamps with gate-driven LDMOS (lateral double-diffused MOS).

• Journal of Navigation and Port Research
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• v.34 no.10
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• pp.807-815
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• 2010

This study analyzed the correlation between RFID acceptance intention and application, and as a result, extracted the technical stability, system quality and security of RFID as factors that affect the intention of receiving RFID in container terminal gate through preliminary research. This analysis was done on individuals engaged in container terminals which are in operation by adopting RFID in container terminal gate presently, and by distributing totally 255 copies of questionnaire survey, 248 copies were collected. As a result of statistical analysis of this study, the following conclusions were made: First, the technical stability of RFID acceptance in container terminal gate was not statistically significantly high. Second, the system quality and the security of RFID acceptance in container terminal gate were statistically significantly high. Finally, container terminal gate RFID technology acceptance intention was statistically significantly high in application performance.