• Proceedings of the IEEK Conference
• /
• 2001.06b
• /
• pp.233-236
• /
• 2001

We have designed and fabricated ASK modulator MMIC operating at 5.8GHz for OBE used in AGPS (Automatic Gate Passing System). ASK modulator MMIC was designed to apply a sing1e supply voltage of 3V to the drain in order to decrease ACP (Adjacent Channel Power). The measurement result of this chip exhibits on/off characteristic over 30dB. The design parameters are optimized through ADS simulation tool. The layouts and fabrication o( ASK Modulator MMIC were designed and fabricated by using ETRI 0.5${\mu}{\textrm}{m}$ MESFET library. The chip sizes were 1mm $\times$1mm. The performance analysis of the implemented ASK Modulator based on the design parameters is accomplished.

• Journal of the Korean Society of Safety
• /
• v.34 no.1
• /
• pp.21-26
• /
• 2019

This paper is purposed to develop hardware for controlling abnormal temperature that can occur environment and component itself in PCS. In order to be purpose, the hardware which is four part(sensing, PLC, monitoring and output) keep detecting temperature for critical components of PCS and can control the abnormal temperature. Apply to the hardware, it is selected to PV power generation facilities of 20 kW in Cheong-ju city and measured the data for one year in 2017. Through the temperature data, it is found critical components of four(discharge resistance, DC capacitor, IGBT, DSP board) and entered the setting value for operating the fan. The setting values for operating the fan are up to $130^{\circ}C$ in discharge resistance, $60^{\circ}C$ in DC capacitor, $55^{\circ}C$ in IGBT and DSP board. The hardware is installed at the same PCS(20 kW in Cheong-ju city) in 2018 and the power generation output is analyzed for the five days with the highest atmospheric temperature(Clear day) in July and August in 2017 and 2018 years. Therefore, the power generation output of the PV system with hardware increased up to 4 kWh.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.43 no.5 s.347
• /
• pp.128-136
• /
• 2006

In this paper, design and implement 50W Doherty power amplifiers for 3GPP repeater and base station transceiver system. Efficiency improvement and high power property of ideal Doherty power amplifier is distinguishable; however bias control for implementation of Doherty(GDCHD) amplifier is difficult. To solve the problem, therefore, GDCHD(Gate and Drain Control Hybrid Doherty) power amplifier is embodied to drain bias adjustment circuit to Doherty power amplifier with gate bias adjustment circuit. Experiment result shows that $2.11{\sim}2.17\;GHz$, 3GPP operating frequency band, with 57.03 dB gain, PEP output is 50.30 dBm, W-CDMA average power is 47.01 dBm, and -40.45 dBc ACLR characteristic in 5MHz offset frequency band. Each of the parameter satisfied amplifier specification which we want to design. Especially, GDCHD power amplifier shows proper efficiency performance improvement in uniformity ACLR than Doherty power amplifier.

• Proceedings of the KIEE Conference
• /
• 2001.07b
• /
• pp.1091-1093
• /
• 2001

The power semiconductor is widely used in the power plant or industrial field because of genealization and enlargement. It has been controlled and operated according to its own control method. Especially in case of Power plant, it plays a major role in AVR(Automatic Voltage Regulator) or electro chlorination control circuits. Generally, they used in Analog control system at above field. But each SCR current value is different because of load unbalance or switching characteristic variations, it may cause power plant unit trip or system disorder according to SCR element burn out or bad operating condition. Therefore, in this paper a development of 3 phase current balance control algorithm is described. it gets over the past analog control system limit, controls SCR gate firing angle for 3 phase current balance.

• Journal of the Korean Society of Industry Convergence
• /
• v.2 no.2
• /
• pp.103-108
• /
• 1999

The paper describes a implementation of space vector pulse-width modulation voltage source inverter and interfacing of DSP using field programmable gate array(FPGA) for a induction motor vector control system. The implemented chip is included logic circuits for SVPWM, dead time compensation and speed detection using Quick Logic, QLl6X24B. The maximum operating frequency and delay time can be set to 110MHz and 6 nsec. The designed Application Specific Integrated Circuit(ASIC) for SVPWM can be incorporated with a digital signal processing to provide a simple and effective solution for high performance induction motor drives with a voltage source inverter. Simulation and implementation results are shown to verify the usefulness of ASIC in a motor drive system and power electronics applications.

• Electrical & Electronic Materials
• /
• v.9 no.10
• /
• pp.1027-1032
• /
• 1996

The auto-illumination controller for office, residence, and so on was studied. The system consists of parts of a power supply, a signal oscillator, a lamp controller and two kinds of sensor. The lamp controller has two thyristors triggered by the IR sensor(SCRI) and CdS sensor(SCR2) respectively, When the illuminance around this system is higher than operating value of its sensor, lamp is turned off automatically. Otherwise, the light of lamp gets dim by CdS sensor. In case IR sensor senses the body heat of people around itself, the illuminance of the lamp gets maximum. The illuminance of the lamp can be changed dimmly by control of the variable resistor (RV) connected with SCR2 in series. The turning - on time of the lamp can be also controlled using a variable resistor(Rt) connected with a signal oscillator in parallel. Changing resistance Rt changes the time constant(.tau.), which triggers the gate of SCR2. Though people left the surrounding of lamp, the lamp keeps light for a while.

• Convergence Security Journal
• /
• v.17 no.2
• /
• pp.41-51
• /
• 2017

The explosive increase in the range of Internet usage gradually makes the speed and capacity of network high-speed, rapidly evolving it into mass storage. Accordingly, network equipment such as switch and router are coping with it through hardware-based rapid technological evolution, but as the technological development of the most basic and essential network security system in the hyper-connected society requires frequent alterations and updates about the security issues and signatures of tens of thousands, so it is not easy to overcome the technical limitations based on the software. In this paper, to improve problems in installing and operating such anti-DDoS devices, we propose a Hi-DPI algorithm best reflecting the hardware characteristics and parallel processing characteristics of FPGA (Field Programmable Gate Array), and would verify the practicality.

• Transactions on Electrical and Electronic Materials
• /
• v.18 no.4
• /
• pp.229-236
• /
• 2017

This paper deals with the design and implementation of an efficient topology for cascaded multilevel inverters with reduced part counts. In the proposed design, a well-established basic unit is first developed. The series extension of this unit results in the formation of the proposed multilevel inverter. The proposed design minimizes the number of power electronic components including insulated-gate bipolar transistors and gate driver circuits, which in turn cuts down the size of the inverter assembly and reduces the operating power losses. An explicit control strategy with enhanced device efficiency is also acquired. Thus, the part count reductions enhance not only the economical merits but also the technical features of the entire system. In order to accomplish the desired operational aspects, three algorithms are considered to determine the magnitudes of the dc voltage sources effectively. The proposed topology is compared with the conventional cascaded H-bridge multilevel inverter topology, to reflect the merits of the presented structure. In continue, both the analytical and experimental results of a cascaded 31-level structure are analyzed. The obtained results are discussed in depth, and the exemplary performance of the proposed structure is corroborated.

• Journal of Sensor Science and Technology
• /
• v.30 no.4
• /
• pp.236-242
• /
• 2021

In this paper, we report the fabrication of the tip-on-gate of a field-effect-transistor (ToGoFET) probe using a standard complementary metal-oxide-semiconductor (CMOS) process and the performance evaluation of the fabricated probe. After the CMOS process, I-V characteristic measurement was performed on the reference MOSFET. We confirmed that the ToGoFET probe could be operated at a gate voltage of 0 V due to channel ion implantation. The transconductance at the operating point (Vg = 0 V, Vd = 2 V) was 360 ㎂/V. After the fabrication process was completed, calibration was performed using a pure metal sample. For sensitivity calibration, the relationship between the input voltage of the sample and the output current of the probe was determined and the result was consistent with the measurement result of the reference MOSFET. An oxide sample measurement was performed as an example of an application of the new ToGoFET probe. According to the measurement, the ToGoFET probe could spatially resolve a hundred nanometers with a height of a few nanometers in both the topographic image and the ToGoFET image.

• Journal of Broadcast Engineering
• /
• v.2 no.1
• /
• pp.8-15
• /
• 1997

In this paper, a real-time operating Motion Picture Experts Group-1 (MPEG-1) audio encoder system is implemented using a TMS320C31 Digital Signal Processor (DSP) chip. The basic operation of the MPEG-1 audio encoder algorithm based on audio layer-2 and psychoacoustic model-1 is first verified by C-language. It is then realized using the Texas Instruments (Tl) assembly in order to reduce the overall execution time. Finally, the actual BSP circuit board for the encoder system is designed and implemented. In the system, the side-modules such as the analog-to-digital converter (ADC) control, the input/output (I/O) control, the bit-stream transmission from the DSP board to the PC and so on, are utilized with a field programmable gate array (FPGA) using very high speed hardware description language (VHDL) codes. The complete encoder system is able to process the stereo audio signal in real-time at the sampling frequency 48 kHz, and produces the encoded bit-stream with the bit-rate 192 kbps. The real-time operation capability of the encoder system and the good quality of the decoded sound are also confirmed using various types of actual stereo audio signals.