• Journal of IKEEE
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• v.24 no.1
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• pp.364-367
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• 2020

This paper presents the off-grid PV-ESS system of sequential voltage control method applied to OR logic gate. The conventional off-grid PV-ESS system with the low-voltage series connection has problems due to capacity expansion. To solve these problems, this paper proposes a noble PV-ESS system with high efficiency and low cost by applying sequential voltage control technique of the high-voltage series connection of analog circuit type. The input voltage of DC to AC inverter can be converted from the low-voltage by the combinations of series connection of the conventional cascaded 24V solar cell unit modules to the high-voltage of 384V in battery. The output voltage of the battery was 384V as the each input voltage of three phase DC to AC inverter, and the each output voltage of three phase 10kW DC to AC inverter is designed to be AC380V@60Hz as the line to line rms voltage value. To prove the validity of the theoretical analysis by PSIM simulation, the operating characteristics of sequential voltage control system with OR logic gate were confirmed through experiment results.

• Nuclear Engineering and Technology
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• v.50 no.6
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• pp.860-868
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• 2018

This article presents a new design of earthquake instrumentation that is suitable for quick decision-making after the seismic event at the nuclear power plant (NPP). The main objective of this work is to ensure more availability of the NPP by expediting walk-down period when the seismic wave is incident. In general, the decision-making to restart the NPP after the seismic event requires more than 1 month if an earthquake exceeds operating basis earthquake level. It affects to the plant availability significantly. Unnecessary shutdown can be skipped through quick assessments of operating basis earthquake, safe shutdown earthquake events, and damage status to structure, system, and components. Multidecision parameters such as cumulative absolute velocity, peak ground acceleration, Modified Mercalli Intensity Scale, floor response spectrum, and cumulative fatigue are discussed. The implementation scope on the field-programmable gate array platform of this work is limited to cumulative absolute velocity, peak ground acceleration, and Modified Mercalli Intensity. It can ensure better availability of the plant through integrated decision-making process by automatic assessment of NPP structure, system, and components.

• ETRI Journal
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• v.38 no.4
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• pp.645-653
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• 2016

This paper demonstrates the performance of a metal-substrate power module with multiple fabricated chips for a high current electrical application, and evaluates the proposed module using a 1.5-kW sinusoidal brushless direct current (BLDC) motor. Specifically, the power module has a hybrid structure employing a single-layer heat-sink extensible metal board (Al board). A fabricated motor driver IC and trench gate DMOSFET (TDMOSFET) are implemented on the Al board, and the proper heat-sink size was designed under the operating conditions. The fabricated motor driver IC mainly operates as a speed controller under various load conditions, and as a multi-phase gate driver using an N-ch silicon MOSFET high-side drive scheme. A fabricated power TDMOSFET is also included in the fabricated power module for three-phase inverter operation. Using this proposed module, a BLDC motor is operated and evaluated under various pulse load tests, and our module is compared with a commercial MOSFET module in terms of the system efficiency and input current.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.6
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• pp.37-43
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• 1999

Two-way addressing method has been proposed for efficient VLSI implementation of Euclidean calculation circuit for pipelined Reed-Solomon decoder. This new circuit is operating with single clock while exploiting maximum parallelism, and uses register addressing instead of register shifting to minimize the switching power. Logic synthesis shows the circuit with the new scheme takes 3,000 logic gates, which is about 40% reduction from the previous 5,000 gate implementation. Computer simulation also shows the power consumption is about 3mW. The previous implementation with multiple clock consumed about 5mW.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.35 no.12
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• pp.541-554
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• 1986

This paper presents the results of driving performance analysis of permanent magnet synchronous motor using a microprocessor based control system. The system consists of three phase power transistor inverters, three phase controlled rectifier, three central processing units, and sensors. The three CPUs are, respectively, used to generate PWM control signals for the inverter generating three phase sine wave, to generate the gate control signals for firing the converter, and to supervise other two CPUs. The supervisor is used to compute PI control algtorithm to three phase reference sine wave for the inverter. It is also used to maintain a constant voltage frequency ratio for the converter operating as a constant torque controller. The inverter CPU retrieves precomputed PWM patterns from look up tables because of computation speed limitations found in almost available microprocessors. The converter CPU also retrieves precomputed gate control patterns from another look-up tables. For protecting the control ststem from any damage by extraordinary over currents, the supervisor receives the data from current sensor, CT, and break down the CB to isolate the circuits from source. A resolver has a good performance characteristics of overall speed range, especially on low speed range. Therefor the speed control accuracy is impoved. The microprocessor based PM synchronous motor control system, thus, has many advantages such as constant torque characteristics, improvement of wave, limitation on extraordinary over currents, improvement of speed control accuracy, and fast response speed control using multi-CPU and look-up tables.

• Journal of the Korean Society of Systems Engineering
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• v.17 no.2
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• pp.49-60
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• 2021

The Core Protection Calculator System (CPCS) is vital for plant safety as it ensures the required Specified Acceptance Fuel Design Limit (SAFDL) are not exceeded. The CPCS generates trip signals when Departure from Nucleate Boiling Ratio (DNBR) and Local Power Density (LPD) exceeds their predetermined setpoints. These setpoints are established based on the operating margin from the analysis that produces the SAFDL values. The goal of this research is to create a simplified CPCS that optimizes operating margin for I-SMRs. Because the I-SMR is compact in design, instrumentation placement is a challenge, as it is with Ex-core detectors and RCP instrumentation. The proposed CPCS addresses the issue of power flux measurement with In-Core Instrumentation (ICI), while flow measurement is handled with differential pressure transmitters between Steam Generators (SG). Simplification of CPCS is based on a Look-Up-Table (LUT) for determining the CEA groups' position. However, simplification brings approximations that result in a loss of operational margin, which necessitates compensation. Appropriate compensation is performed based on the result of analysis. FPGAs (Field Programmable Gate Arrays) are presented as a way to compensate for the inadequacies of current systems by providing faster execution speeds and a lower Common Cause Failure rate (CCF).

• Journal of information and communication convergence engineering
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• v.6 no.2
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• pp.177-181
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• 2008

The more improved the Internet and the information technology, the stronger cryptographic system is required which can satisfy the information security on the platform of personal hand-held devices or smart card system. This paper introduces a case study of designing an elliptic curve cryptographic processor of a high performance that can be suitably used in a wireless communicating device or in an embedded system. To design an efficient cryptographic system, we first analyzed the operation hierarchy of the elliptic curve cryptographic system and then implemented the system by adopting a serial cell multiplier and modified Euclid divider. Simulation result shows that the system was correctly designed and it can compute thousands of operations per a second. The operating frequency used in simulation is about 66MHz and gate counts are approximately 229,284.

• Proceedings of the KIEE Conference
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• 2003.11c
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• pp.653-656
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• 2003

We have designed embedded web sewer system and ported Linux operating system version 2.4.5 at our system. And then We implemented to control and monitor widely separated hardware and implemented to monitor widely separated image using CMOS image sensor HV7131B. Web server is the Boa web server with General Public License. We designed for this system using of Intel's SA1110 ARM core base processor and connecting input and output device at GPIO port of SA1110. Device driver of General purpose I/O for Embedded Linux OS is designed. And then the application program controlling driver is implemented to use of common gate interface C language. User is available to control and monitor at client PC. This method have benefit to reduce the Expenditure of hardware design and development time against PC base system and have various and capacious application against firmware base system.

• The Proceedings of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.7 no.3
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• pp.57-66
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• 1993

This research proposes a high frequency series resonant inverter consisting of equivalent half - bridge model in combination with two L-C linked full-bridge inverter circuits using MOSFET. As a output power control strategy, the sequential gate control method is applied. Also, analysis of operating MODE and state equation is described. From the computer simulation results, the inverters and devices can be shared properly voltage and current rating of the system in accordance with series and parallel operations. And it is confirmed that the proposed system has very stable performance.

• Journal of Electrical Engineering and Technology
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• v.10 no.4
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• pp.1655-1666
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• 2015

This paper proposes a new approach of Field Programmable Gate Array (FPGA) controlled digital implementation of shunt active power filter (SAPF) under steady state and dynamic operations. Typical implementations of SAPF uses microprocessor and digital signal processor (DSP) but it limited for complex algorithm structure, absence of feedback loop delays and their cost can be exceed the benefit they bring. In this paper, the hardware resources of an FPGA are configured and implemented in order to overcome conventional microcontroller or digital signal processor implementations. This proposed FPGA digital implementation scheme has very less execution time and boosts the overall performance of the system. The FPGA controller integrates the entire control algorithm of an SAPF, including synchronous reference frame transformation, phase locked loop, low pass filter and inverter current controller etc. All these required algorithms are implemented with a single all-on chip FPGA module which provides freedom to reconfigure for any other applications. The entire algorithm is coded, processed and simulated using Xilinx 12.1 ISE suite to estimate the advantages of the proposed system. The coded algorithm is also defused on a single all-on-chip Xilinx Spartan 3A DSP-XC3SD1800 laboratory prototype and experimental results thus obtained match with simulated counterparts under the dynamic state and steady state operating conditions.