• 제목/요약/키워드: Gate Location Design

검색결과 76건 처리시간 0.024초

복합힌지를 갖는 차량용 정션박스의 게이트 위치설계 (Gate Location Design of an Automobile Junction Box with Integral Hinges)

  • 김홍석
    • 소성∙가공
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    • 제12권2호
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    • pp.134-140
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    • 2003
  • Polymers such as polypropylene or polyethylene offer a unique feature of producing an integral hinge, which can flex over a million times without causing a failure. With such advantage manufacturing, time and cost required at the assembly stage can be eliminated by injecting the whole part as one piece. However, due to increased fluidity resistance at hinges during molding, several defects such as short shot or premature hinge failure can occur with the improper selection of gate locations. Therefore, it is necessary to optimize flow balancer in injection molding of part with hinges before actually producing molds. In this paper, resin flow patterns depending on several gate positions were investigated by numerical analyses of a simple strip part with a hinge. As a result, we found that the properly determined gate location leads to better resin flow and shorter hesitation time. Finally, injection molding tryouts using a mold that was designed one of the proposed gate systems were conducted using polypropylene that contained 20% talc. The experiment showed that hinges without defects could be produced by using the designed gate location.

자동차용 에어클리너 상부커버 사출성형에서 게이트의 위치 결정 (A Study on Decision of gate location for Injection molding of Automobile air cleaner Upper cover)

  • 장성민;김인수
    • 한국산학기술학회논문지
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    • 제16권7호
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    • pp.4411-4417
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    • 2015
  • 플라스틱 제품의 사출금형을 위한 게이트 위치의 최적 설계는 다양한 설계에 대한 3차원 사출성형 분석으로 도출할 수 있다. 이 논문은 사출금형에서 게이트 위치의 영향에 관한 연구이다. 게이트 위치는 플라스틱 제품의 생산성과 품질에 결정적인 영향을 미친다. 논문의 목적은 사출기를 사용한 자동차 에어 클리너 상부커버의 제조과정 중에 수지충전, 웰드라인, 사출압력에 대한 게이트의 영향을 분석하기 위한 것이다. 따라서 이 논문에서 이러한 문제들을 분석하기 위한 게이트의 위치는 4가지 경우로 변화를 주었다. 논문에서 각각의 게이트 위치 변화를 고려한 CAE 시뮬레이션은 사출금형공정에서 제품에 나타나는 결함의 원인을 예견하기 위하여 수행되었다.

사출성형의 게이트 위치 최적화

  • 임원길;김영일;설권
    • 한국정밀공학회:학술대회논문집
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    • 한국정밀공학회 1996년도 춘계학술대회 논문집
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    • pp.787-791
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    • 1996
  • In injection molding, location of gates have great influence on the quality of plastic parts. Usually, they are located by releated trial and errors of experienced mold designers. In this topic we will present the numerical algorithm for finding the optimal gate locations. Optimization algorithm is devided into two stages. In the first stage, candidated optimal gate locations can be found by geometry of part only; whereas in the next step, more acculate gate locations are selected byiterative computation with optimization part and analysis part. So from the following study, we suggested the modified flow-volume method, which will define the optimal gate locations in injection mold design.

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설계영역 반복축소법에 의한 사출금형의 수지 유동균형을 위한 게이트 위치 최적화 (Optimization of Gate Location for Melt Flow Balancing in Injection Mold Cavity By Using Recursive Design Area Reduction Method)

  • 박종천;이규석;최성일;강진현
    • 한국기계가공학회지
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    • 제12권4호
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    • pp.114-122
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    • 2013
  • This study introduces an optimization methodology for the determination of gate location that ensures the melt flow balance within a part cavity of injection mold. A new sequential direct-search scheme based on the recursive reduction of the designer-specified gate design area is developed, and it is integrated with a commercial flow simulation tool for optimization. To quantify the level of melt flow balance, we employ the maximum difference among the fill times for the melt fronts to reach the boundary elements of part cavity as objective function. The proposed methodology is successfully applied in the case study of melt flow balancing in molding of a bar code scanner model. The result shows that the melt flow balance at the optimized gate positions is significantly improved from that for the initial gate position.

IGBT 배열과 설치 위치에 따른 히트 싱크 방열 성능 (Thermal Performance of a Heat Sink According to Insulated Gate Bipolar Transistor Array and Installation Location)

  • 박승재;윤영찬;이태희;이관수
    • 설비공학논문집
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    • 제30권1호
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    • pp.1-9
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    • 2018
  • Thermal performance of a heat sink for an inverter power stack was analyzed in terms of array and installation location of an Insulated Gate Bipolar Transistor (IGBT). Thermal flow around the heat sink was calculated with a numerical model that could simulate forced convection. Thermal performance was calculated depending on the array and location of high- and low-power IGBTs considering the maximum temperature of IGBT. The optimum array and installation location were found and causes were analyzed based on results of numerical analysis. For the numerical analysis, experiment design considered the installation location of IGBT, ratio of heat generation rates of high- and low-power IGBTs, and velocity of the inlet air as design variables. Based on numerical results, a correlation that could calculate thermal performance of the heat sink was suggested and the maximum temperature of the IGBT could be predicted depending on the installation method.

대면적 고화질 TFT-LCD용 게이트 Driving에 관한 Simulation (Simulations of Gate Driving Schemes for Large Size, High Quality TFT-LCD)

  • 정순신;윤영준;김태형;최종선
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1999년도 하계학술대회 논문집 D
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    • pp.1809-1811
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    • 1999
  • In recent years, attempts have been made to greatly improve the display quality of active-matrix liquid crystal display devices, and many techniques have been proposed to solve such problems as gate delay, feed-through voltage and image sticking. Gate delay is one of the biggest limiting factors for large-screen-size, high-resolution thin-film transistor liquid crystal display (TFT/LCD) design. Many driving method proposed for TFT/LCD progress. Thus we developed gate driving signal generator. Since Pixel-Design Array Simulation Tool (PDAST) can simulate the gate, data and pixel voltages of a certain pixel on TFT array at any time and at any location on an array, the effect of the driving signals of gate lines on the pixel operations can be effectively analyzed.

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게이트 라인 물질의 저항률이 TFT-LCD 화소의 동작에 미치는 영향 (Effects of Resistivity of Gate Line Material on TFT-LCD Pixel Operations)

  • 이영삼;최종선
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 1998년도 춘계학술대회 논문집
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    • pp.321-324
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    • 1998
  • Pixel-Design Array Simulation Tool(PDAST) was used to profoundly the gate signal distortion and pixel changing capability, which are the most critical limiting factors for high-quality TFT-LCDs. Since PDAST can simulate the gate, data and pixel voltages of a certain pixel on TFT array at any time and at any location on an array, the effect of the resistivity of gate line material on the pixel operations can be effectively analyzed. The gate signal delay, pixel charging ratio, level-shift of the pixel voltage were simulated with varying the resis5tivity of the gate line material. The information obtained from this study could be utilized to design the larger area and finer image quality panel.

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Design of Gate System in Injection Molding of a Dashboard by CAMPmold

  • Choi D. S.;Han K. H.;Kim H. S.;Im Y. T.
    • 한국소성가공학회:학술대회논문집
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    • 한국소성가공학회 2003년도 The Korea-Japan Plastics Processing Joint Seminar
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    • pp.33-39
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    • 2003
  • Injection molding is widely used in producing various plastic parts due to its high productivity and the demand for high precision injection molded products is ever increasing. To achieve successful product quality and precision, the design of gating and runner systems in the injection mold is very important since it directly influences melt flow into the cavity. Some defects such as weld lines and overpacking can be effectively controlled with proper selection of gate locations. In the present study, the design of gate locations in injection molding of a dashboard for automobiles was carried out with CAMPmold, a PC-based simulation system for injection molding. A dummy runner was developed to simulate a runner system in order to increase the efficiency of the analysis. The numbers and locations of gates were varied in the present investigation as that an acceptable design was obtained in terms of reduced maximum pressure and clamping force.

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유동해석을 이용한 자동차용 부품(오일팬_DX2E)의 주조방안설계에 대한 사례연구 (A Case Study on Casting Layout Design of Automotive Oil Pan_DX2E Using Computer Simulation)

  • 권홍규
    • 산업경영시스템학회지
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    • 제36권4호
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    • pp.71-76
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    • 2013
  • For a die casting mold, generally, the casting layout design should be considered based on the relation among injection system, casting condition, gate system, and cooling system. Also, the extent or the location of product defects was differentiated according to the various relations of the above conditions. In this research, in order to optimize the casting layout design of an automotive Oil Pan_DX2E, Computer Aided Engineering (CAE) simulation was performed with two layout designs by using the simulation software (AnyCasting). The simulation results were analyzed and compared carefully in order to apply them into the production die-casting mold. During the filling process with two models, internal porosities caused by air entrapments were predicted and also compared with the modification of the gate system and overflow. With the solidification analysis, internal porosities occurring during the solidification process were predicted and also compared with the modified gate system.

대면적 고화질의 TFT-LCD 화소 설계 최적화 및 어레이 시뮬레이션 특성 (Array Simulation Characteristics and TFT-LCD Pixel Design Optimization for Large Size, High Quality Display)

  • 이영삼;윤영준;정순신;최종선
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 1998년도 추계학술대회 논문집
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    • pp.137-140
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    • 1998
  • An active-matrix LCD using thin film transistors (TFT) has been widely recognized as having potential for high-quality color flat-panel displays. Pixel-Design Array Simulation Tool (PDAST) was used to profoundly understand the gate si후미 distortion and pixel charging capability. which are the most critical limiting factors for high-quality TFT-LCDs. Since PDAST can simulate the gate, data and pixel voltages of a certain pixel on TFT array at any time and at any location on an array, the effect of the resistivity of gate line material on the pixel operations can be effectively analyzed. The gate signal delay, pixel charging ratio and level-shift of the pixel voltage were simulated with varying the parameters. The information obtained from this study could be utilized to design the larger area and finer image quality panel.

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