• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.12
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• pp.8-14
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• 2011

The optimal geometry of the gate field plate in AlGaN/GaN-on-Si HEMT has been proposed using two-dimensional device simulation to achieve a high breakdown voltage for a given gate-to-drain distance. It was found that the breakdown voltage was drastically enhanced due to the reduced electric field at the gate corner when a gate field plate was employed. The electric field distribution at the gate corner and the field plate edge was investigated as functions of field plate length and insulator thickness. According to the simulation results, the electric field at the gate corner can be successfully reduced even with the field plate length of 1 ${\mu}m$. On the other hand, when the field plate length is too long, the distance between field plate and drain electrode is reduced below a critical level, which eventually lowers the breakdown voltage. The highest breakdown voltage was achieved with the field plate length of 1 ${\mu}m$. According to the simulation results varying the $SiN_x$ film thickness for the fixed field plate length of 1 ${\mu}m$, the optimum thickness range of the $SiN_x$ film was 200 - 300 nm where the electric field strength at the field plate edge counterbalances that of the gate corner.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.10
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• pp.1-8
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• 2002

C- V method is a means to determine the effective channel length for miniaturized MOSFET's. This method achieves L$_{eff}$ by extracting a unique channel length independent extrinsic overlap length($\Delta$L) at a critical gate bias point. In this paper, we conducted an experiment on two different C-V methods. L$_{eff}$ extracted from experiment is compared with L$_{eff}$ simulated from a two-dimensional (2-D) device simulator, and the accuracy of C-V method for L$_{eff}$ extraction is analyzed.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.12
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• pp.2939-2945
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• 2014

This paper has analyzed the change of threshold voltage for oxide structure of symmetric and asymmetric double gate(DG) MOSFET. The asymmetric DGMOSFET can be fabricated with different top and bottom gate oxide thickness, while the symmetric DGMOSFET has the same top and bottom gate oxide thickness. Therefore optimum threshold voltage is considered for top and bottom gate oxide thickness of asymmetric DGMOSFET, compared with the threshold voltage of symmetric DGMOSFET. To obtain the threshold voltage, the analytical potential distribution is derived from Possion's equation, and Gaussian distribution function is used as doping profile. We investigate for bottom gate voltage, channel length and thickness, and doping concentration how top and bottom gate oxide thickness influences on threshold voltage using this threshold voltage model. As a result, threshold voltage is greatly changed for oxide thickness, and we know the changing trend greatly differs with bottom gate voltage, channel length and thickness, and doping concentration.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.33 no.4
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• pp.281-285
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• 2020

Oxide semiconductor devices have become increasingly important because of their high mobility and good uniformity. The channel length of oxide semiconductor thin film transistors (TFTs) also shrinks as the display resolution increases. It is well known that reducing the channel length of a TFT is detrimental to the current saturation because of drain-induced barrier lowering, as well as the movement of the pinch-off point. In an organic light-emitting diode (OLED), the lack of current saturation in the driving TFT creates a major problem in the control of OLED current. To obtain improved current saturation in short channels, we fabricated indium gallium zinc oxide (IGZO) TFTs with single gate and double gate structures, and evaluated the electrical characteristics of both devices. For the double gate structure, we connected the bottom gate electrode to the source electrode, so that the electric potential of the bottom gate was fixed to that of the source. We denote the double gate structure with the bottom gate fixed at the source potential as the BGFP (bottom gate with fixed potential) structure. For the BGFP TFT, the current saturation, as determined by the output characteristics, is better than that of the conventional single gate TFT. This is because the change in the source side potential barrier by the drain field has been suppressed.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.05a
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• pp.741-744
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• 2014

This paper has analyzed threshold voltage roll-off for bottom gate voltages of asymmetric double gate(DG) MOSFET. Since the asymmetric DGMOSFET is four terminal device to be able to separately bias for top and bottom gates, the bottom gate voltage influences on threshold voltage. It is, therefore, investigated how the threshold voltage roll-off known as short channel effects is reduced with bottom gate voltage. In the pursuit of this purpose, off-current model is presented in the subthreshold region, and the threshold voltage roll-off is observed for channel length and thickness with a parameter of bottom gate voltage as threshold voltage is defined by top gate voltage that off-currnt is $10^{-7}A/{\mu}m$ per channel width. As a result to observe the threshold voltage roll-off for bottom gate voltage using this model, we know the bottom gate voltage greatly influences on threshold voltage roll-off voltages, especially in the region of short channel length and thickness.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.505-508
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• 2004

Gate length dependent data of intrinsic MOSFET equivalent circuit parameters are extracted using a direct extraction technique based on simple 2-port parameter equations. The relatively scalable data with respect to gate length are obtained. These data are verified to be acrurate by observing good correspondence between modeled and measured S-parameters up to 30GHz. These data will be helpful to construct RF scalable MOSFET model.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.13-16
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• 2002

In this study, the electrical characteristics of 100v-Class LDMOSFET for high temperature applicat -ions such as electronic control systems of automo -biles and motor driver were investigated. Measurement data are taken over wide range of temperature(300k-SOOK) and various gate length(1.5 #m-3.0#m, step 0.3). In high temperature condition(>500k), drain current decreased over 30%, and specific on- resistance increased about three times in comparison with room temperature. Moreover, the ratio ROJBV, a figure of merit of the device, increased with increasing temperature.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.43 no.6
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• pp.951-957
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• 1994

We present a new model for the series resistance of inverted-staggered amorphous silicon (a-Si) thin film transistors (TFT's) by employing the current spreading under the source and the drain contacts as well as the space charge limited current model. The calculated results based on our model have been in good agreements with the measured data over a wide range of applied voltage, gate-to-source and gate-to-drain overlap length, channel length, and operating temperature. Our model shows that the contribution of the series resistances to the current-voltage (I-V) characteristics of the a-Si TFT in the linear regime is more significant at low drain and high gate voltages, for short channel and small overlap length, and at low operating temperature, which have been verified successfully by the experimental measurements.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.4
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• pp.40-50
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• 1993

In this paper, MODFET devices with various gate length are simulated using the Monte-Carlo method. The number of superparticle is 5000 and the Poisson equation is solved to obtain field distribution. The structure of MODFET is n-AlGaAs/i-AlGaAs/iGaAs and doping concentration of n-AlGaAs layer is 1${\times}10^{17}/cm^{3}$ and the thickness is 500.angs., and the thickness of i-AlGaAs is 50$\AA$. The devices with gate length 0.2$\mu$m, 0.5$\mu$m, 1.0$\mu$m respctively are simulated and the current-voltage curves and transport characteristics of that devices are obtained. Occupancy of each subband and electron energy distribution and conduction energy band in channel have been analyzed to obtain transport characteristics, and particles transposed from source to drain have been analyzed to current-voltage curves. Current level is highest for the device of Lg=0.2$\mu$m and transconductance of this device is 310mS/mm.

• Journal of information and communication convergence engineering
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• v.10 no.2
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• pp.200-204
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• 2012

This study has presented the analysis of breakdown voltage for a double-gate metal-oxide semiconductor field-effect transistor (MOSFET) based on the doping distribution of the Gaussian function. The double-gate MOSFET is a next generation transistor that shrinks the short channel effects of the nano-scaled CMOSFET. The degradation of breakdown voltage is a highly important short channel effect with threshold voltage roll-off and an increase in subthreshold swings. The analytical potential distribution derived from Poisson's equation and the Fulop's avalanche breakdown condition have been used to calculate the breakdown voltage of a double-gate MOSFET for the shape of the Gaussian doping distribution. This analytical potential model is in good agreement with the numerical model. Using this model, the breakdown voltage has been analyzed for channel length and doping concentration with parameters such as projected range and standard projected deviation of Gaussian function. As a result, since the breakdown voltage is greatly changed for the shape of the Gaussian function, the channel doping distribution of a double-gate MOSFET has to be carefully designed.