• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.481-482
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• 2006

We fabricated pentacene organic thin film transistor with good uniformity. And we extracted contact resistance in organic thin film transistors from the plot of the inverse of drain current versus channel length by extrapolating the curve to a channel length of zero, and multiplying by drain-source voltage. Extracted contact resistance is about $70K{\Omega}$ at gate-drain voltage of -20 V

• Journal of information and communication convergence engineering
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• v.8 no.4
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• pp.449-452
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• 2010

We have analyzed channel doping and dimensions(channel length, width and thickness) for the optimum subthreshold characteristics of DG(Double Gate) MOSFET based on the model of MicroTec 4.0. Since the DGMOSFET is the candidate device to shrink short channel effects, the determination of design rule for DGMOSFET is very important to develop sub-100nm devices for high speed and low power consumption. As device size scaled down, the controllability of dimensions and oxide thickness is very low. We have analyzed the short channel effects for the variation of channel dimensions, and found the design conditions of DGMOSFET having the optimum subthreshold characteristics for digital applications.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.1189-1192
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• 2009

Short channel a-Si:H TFT devices with Cu electrodes have been investigated. Short channel TFTs are defined by new plasma etch process. When the channel length becomes shorter, the TFT characteristics (threshold voltage, off current, sub threshold voltage, etc.,) are degraded. These degraded characteristics can be improved through the hydrogen plasma treatment and new gate insulator structure. Using these processes, 15.0 inch XGA LCD panel was fabricated successfully where the channel length of the TFT devices was about 2.5 micrometers.

• Proceedings of the KIEE Conference
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• 1995.07b
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• pp.931-933
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• 1995

In this paper, we develop protype of wierless recognition system using low frequency. Application of this system is very broad. Namely, High-way toll gate, animal management, parking system and industral automation et al. This system is composed of controller, decoder and tag. Controller is personal PC, decoder is signal module and tag is mobile corresponder module. Modulation is ASK, 4,800bps, frequency is 120/60kHz and transmission length is about 80cm. And now we study improvement of stability, low power consumption, compact of tag and transmission length improvement.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.6
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• pp.22-27
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• 1997

This paper propose a novel VLSI architecture for a multiplierless FIR filter chip providing variable-length taps. To change the number of taps, we propose two special features called a data-reuse structure and a recurrent-coefficient scheme. These features consist of several MUXs and registers and reduce the number of gates over 20% compared with existing chips using an address generation unit and a modulo unit. Since multipliers occupy large VLSI area, a multiplierless filter chip meeting real-time requirement can save large area. We propose a modified bit-serial multiplication algorithm to compute two partial products in parallel, and thus, the proposed filter is twice faster and has smaller hardware than previous multiplierless filters. We developed VHDL models and performed logic synthesis using the 0.8.mu.m SOG (sea-of-gate) cell library. The chip has only 9,507 gates, was fabricated, and is running at 77MHz.

• Electrical & Electronic Materials
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• v.8 no.6
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• pp.708-714
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• 1995

We have discussed the buried-channel(BC) behavior through the subthreshold characteristics of submicron PMOSFET device fabricated with twin well CMOS process. In this paper, we have guessed the initial conditions of ion implantation using process simulation, obtained the subthreshold characteristics as a function of process parameter variation such as threshold adjusting ion implant dose($D_c$), channel length(L), gate oxide thickness($T_ox$) and junction depth of source/drain($X_j$) using device simulation. The buried channel behavior with these process prarameter variation were showed apparent difference. Also, the fabricated pMOSFET device having different channel length represented good S.S value and low leakage current with increasing drain voltage.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.4B
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• pp.365-371
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• 2002

In this paper, the fabricated power PHEMT devices for millimeter-wave that is below a gate-length of 0.2 $\mu\textrm{m}$ using electronic beam lithography technologies, and the DC and frequency characteristics and an output power characteristics were Measured at the various bias conditions. The unit process that is used in PHEMT's manufacture used that low-resistance ohmic contact, air-bridge and back-side lapping process technologies, and so on. The fabricated power PHEMT have an S521 gain of 4 dB and a maximum transconductance(gm) of 317 mS/mm, an unilateral current gain(fT) of 62 GHz, a maximum oscillation frequency(fmax) of 120 GHz at 35 GHz, and a maximum power output(Pmax) of 16 dBm, a power gain(GP) of 4 dB and a drain efficiency(DE) of 35.5 %.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.12
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• pp.656-664
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• 2007

Field-Programmable Gate Arrays (FPGAs) are a revolutionary new type of user-programmable integrated circuits that provide fast, inexpensive access to customized VLSI. However, as the target application speed increases, power-consumption and wire-delay on interconnection become more critical factors during programming an FPGA. Especially, the interconnection of the FPGA consumes 65% of the total FPGA power consumption. A previous research show that if the length of interconnection is shirked, power-consumption can be reduced because an interconnection has a lot of effect on power-consumption. For solving this problem that reducing the number of wires routed, the three dimension FPGA is proposed. However, this structure physical wires and an area of switches is increased by making topology complex. This paper propose a novel FPGA architecture that modifies the three dimension FPGA and compare the number of interconnection of Virtex II and 3D FPGA with the proposed FPGA architecture using the FPGA Editor of Xilinx ISE and a global routing and length estimation program.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.2
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• pp.128-135
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• 2013

This letter presents the MISHFET with si-doped AlGaN/GaN heterostructure for power amplifier. The device grown on 6H-SiC(0001) substrate with a gate length of 180 nm has been fabricated. The fabricated device exhibited maximum drain current density of 837 mA/mm and peak transconductance of 177 mS/mm. A unity current gain cutoff frequency was 45.6 GHz and maximum frequency of oscillation was 46.5 GHz. The reported output power density was 1.54 W/mm and A PAE(Power Added Efficiency) was 40.24 % at 9.3 GHz.

• Journal of Korea Foundry Society
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• v.27 no.4
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• pp.153-158
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• 2007

Molten metal flow in vacuum die casting was characterized by a numerical analysis. The VOF method was used to simulate the filling behaviors of molten metal during filling process. The various vacuum degrees of no vacuum(760 mmHg), 650, 500, 250 and 60mmHg were artificially applied in cavity. And the filling behaviors of molten metal with the applied vacuum conditions were simulated and compared with those of experiment. The results showed that molten metal was partially filled into cavity when vacuum was applied and the filling length of molten metal in cavity was increased with increasing applied reduced pressure in cavity. Also, the simulated filling behaviors of molten metal were apparently similar to those of experiment, indicating the numerical analysis developed in this study was highly effective. Through the result of fluid flow simulation, both relation equations of filling length and filling velocity with the variation of pressure conditions in cavity were calculated respectively and the internal gas contents of casting was significantly reduced by the modification of vacuum gate system.