• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.10A
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• pp.1579-1587
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• 1999

Bias-dependent noise models of $0.2\mu\textrm{m}$ gate length P-HEMT's which are scalable with gate width are proposed. To predict S-parameters of the P-HEMT's the intrinsic parameters except for $\tau$ subtracted the offsets introduced in this paper are normalized to the gate width and then scaled. The small-signal model parameters are expressed as fitting functions of the drain current to $\textrm{I}_{dss}$ ratio and gate width. In addition, to estimate accurately noise parameters the noise temperature $\textrm{T}_{g}$ of the intrinsic resistance, the equivalent noise conductance $\textrm{G}_{ni}$ of the gate current noise source, and the equivalent noise conductance $\textrm{G}_{no}$ of the drain current noise source are adopted as the noise model parameters. The extracted values of $\textrm{T}_{g}$ are nearly independent of drain current and gate width and their average is around the ambient temperature. The extracted values of $\textrm{G}_{ni}$ are small enough to be neglected to the circuit characteristics. From the comparison of the noise model with only $\textrm{G}_{no}$ and that having $\textrm{T}_{g}$, $\textrm{G}_{ni}$ and $\textrm{G}_{no}$ to the measured data it is fund that even the former model is in good agreement with the measured noise parameters. Thus, from a practical point of view the noise model having only the drain current noise source is confirmed as a scalable bias-dependent model.

• Journal of electromagnetic engineering and science
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• v.1 no.1
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• pp.73-77
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• 2001

We studied the fabrication of GaAs-based pseudomorphic high electron mobility transistors(PHEMT`s) for the purpose of millimeter- wave applications. To fabricate the high performance GaAs-based PHEMT`s, we performed the simulation to analyze the designed epitaxial-structures. Each unit processes, such as 0.1 m$\mu$$\Gamma$-gate lithography, silicon nitride passivation and air-bridge process were developed to achieve high performance device characteristics. The DC characteristics of the PHEMT`s were measured at a 70 $\mu$m unit gate width of 2 gate fingers, and showed a good pinch-off property ($V_p$= -1.75 V) and a drain-source saturation current density ($I_{dss}$) of 450 mA/mm. Maximum extrinsic transconductance $(g_m)$ was 363.6 mS/mm at $V_{gs}$ = -0.7 V, $V_{ds}$ = 1.5 V, and $I_{ds}$ =0.5 $I_{dss}$. The RF measurements were performed in the frequency range of 1.0~50 GHz. For this measurement, the drain and gate voltage were 1.5 V and -0.7 V, respectively. At 50 GHz, 9.2 dB of maximum stable gain (MSG) and 3.2 dB of $S_{21}$ gain were obtained, respectively. A current gain cut-off frequency $(f_T)$ of 106 GHz and a maximum frequency of oscillation $(f_{max})$ of 160 GHz were achieved from the fabricated PHEMT\\`s of 0.1 m$\mu$ gate length.h.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.7
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• pp.1393-1398
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• 2009

Conventionally, etching is first considered for microelectronics fabrication process and is specially important in process of a-Si:H thin film transistor for LCD. In this paper, we stabilize properties of device by development of wet and dry etching process. The a-Si:H TFTs of this paper is inverted staggered type. The gate electrode is lower part. The gate electrode is formed by patterning with length of 8 ${\mu}$m${\sim}$16 ${\mu}$m and width of 80${\sim}$200 ${\mu}$m after depositing with gate electrode (Cr) 1500 ${\AA}$under coming 7059 glass substrate. We have fabricated a-SiN:H, conductor, etch-stopper and photo resistor on gate electrode in sequence, respectively. The thickness of these thin films is formed with a-SiN:H (2000 ${\mu}$m), a-Si:H(2000 ${\mu}$m) and n+a-Si:H (500 ${\mu}$m), We have deposited n-a-Si:H, NPR(Negative Photo Resister) layer after forming pattern of Cr gate electrode by etch-stopper pattern. The NPR layer by inverting pattern of upper gate electrode is patterned and the n+a-Si:H layer is etched by the NPR pattern. The NPR layer is removed. After Cr layer is deposited and patterned, the source-drain electrode is formed. In the fabricated TFT, the most frequent problems are over and under etching in etching process. We were able to improve properties of device by strict criterion on wet, dry etching and cleaning process.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.30 no.4
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• pp.282-285
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• 2019

A 100-nm gate-length metamorphic high electron mobility transistor(mHEMT) with a T-shaped gate was fabricated using a two-step gate recess and characterized for DC and microwave performance. The mHEMT device exhibited DC output characteristics having drain current($I_{dss}$), an extrinsic transconductance($g_m$) of 1,090 mS/mm and a threshold voltage($V_{th}$) of -0.65 V. The $f_T$ and $f_{max}$ obtained for the 100-nm mHEMT device were 190 and 260 GHz, respectively. The developed mHEMT will be applied in fabricating W-band monolithic microwave integrated circuits(MMICs).

• Journal of Adhesion and Interface
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• v.23 no.2
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• pp.53-58
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• 2022

Here, the surface characteristics of the dielectric were controlled by introducing the self-assembled monolayers (SAMs) as the intermediate layers on the surface of the AlOx dielectric, and the electrical performances of the organic charge modulated transistor (OCMFET) were significantly improved. The organic intermediate layer was applied to control the surface energy of the AlOx gate dielectric acting as a capacitor plate between the control gate (CG) and the floating gate (FG). By applying the intermediate layers on the gate dielectric surface, and the field-effect mobility (μ_OCMFET) of the OCMFET devices could be efficiently controlled. We used the four kinds of SAM materials, octadecylphosphonic acid (ODPA), butylphosphonic acid (BPA), (3-bromopropyl)phosphonic acid (BPPA), and (3-aminopropyl)phosphonic acid (APPA), and each μ_OCMFET was measured at 0.73, 0.41, 0.34, and 0.15 cm2V-1s-1, respectively. The results could be suggested that the characteristics of each organic SAM intermediate layer, such as the length of the alkyl chain and the type of functionalized end-group, can control the electrical performances of OCMFET devices and be supported to find the optimized fabrication conditions, as an efficient sensing platform device.

• Journal of the Korean Institute of Telematics and Electronics
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• v.18 no.4
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• pp.43-48
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• 1981

The Cdse TFTs with SiO gate insulator layer have been fabricated with vacum evaporatim technique. The effects of semiconductor thickness and drain-source channel length on the electrical propertis have been investigated. The TFTs with 1000$\AA$ SiO insulator, 1500 $\AA$ CdSe semiconductor layer and 40$\mu$m chammel length showed the best characteristics.

• Proceedings of the KIEE Conference
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• 1992.07b
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• pp.825-828
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• 1992

In this paper, a Hybrid method for an effective channel length($L_{eff}$) on lightly doped drain(LDD) MOSFET's is proposed. In order to investigate the difference of the gate bias and substrate bias defendence of the $L_{eff}$ among various LDD structures, the $L_{eff}$ of the LDD's are extensively examined using simulations and measurement. one group is proposed for conventional MOSFET and the other group Is proposed for LDD MOSFET. It is shown that the $V_{bs}$-dependence of the n-region is different from $V_{gs}$-dependence of it.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.505-508
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• 2006

Self-heating induced device degradation and its width/length (W/L) dimension dependence were studied in p-type polycrystalline silicon (poly-Si) thin film transistors (TFTs). Negative channel conductance was observed under high power region of output curve, which was mainly caused by hole trapping into gate oxide and also by trap state generation by self-heating effect. Self-heating effect became aggravated as W/L ratio was increased, which was understood by the differences in heat dissipation capability. By reducing applied power density normalized to TFT area, self-heating induced degradation could be reduced.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.145-148
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• 2001

In this paper, polycrystalline silicon thin film transistor using by Solid Phase Crystallization(SPC) were fabricated, and these devices were measured and analyzed the electrical output and transfer characteristics along to DC voltage stress. The transfer characteristics of polycrystalline silicon thin film transistor depended on drain and gate voltages. Threshold voltage is high with long channel length and narrow channel width. And output characteristics of polycrystalline silicon thin film transistor flowed abruptly much higher drain current. The devices induced electrical stress are decreased drain current. At last, field effect mobility is the faster as channel length is high and channel width is narrow.

• Proceedings of the Korean Society for Technology of Plasticity Conference
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• 2000.04a
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• pp.171-178
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• 2000

In order to evaluate the tensile behaviors of hoop direction for the nuclear fuel cladding tubes the shapes of specimen and jig fixtures for the ring test are decided with various conditions under the elastic-large plastic deformations. The axial displacement of the jig cylinders is converted to the circumferential direction elongations of specimen. The stress distributions on specimen are depended on the radii and locations of specimen and jig size and central angle. Therefore we calculated the stress distributions and decided the optimum shapes to get the uniform stress in the area of specimen gage length. Form the analysis the stress distributions in gate area are reviewed with the radii and location of specimen notch and the central angle of jig cylinder,. The optimum shapes of specimen and jig are proposed to the clad tube having 10.62 mm in diameter and 0.63mm in thickness for 16x16 PWR nuclear fuel assembly.