• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.2
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• pp.95-102
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• 2001

Nano-scale gate length MOSFET devices require extremely shallow source/drain eftension region with junction depth of 20∼30nm. In this work, 20nm $n^{+}$-p junctions that are realized by using this $As_{2}^{+}$ low energy ($\leq$10keV) implantation show the lower sheet resistance of the $1.0k\Omega$/$\square$ after rapid thermal annealing process. The $As_{2}^{+}$ implantation and RTA process make it possible to fabricate the nano-scale NMOSFET of gate length of 70nm. $As_{2}^{+}$ 5 keV NMOSFET shows a small threshold voltage roll-off of 60mV and a DIBL effect of 87.2mV at 100nm gate length devices. The electrical characteristics of the fabricated devices with the heavily doped and abrupt $n^{+}$-p junctions ($N_{D}$〉$10^{20}$$cm^{-3}$, $X_{j}$$\leq$20nm) suggest the feasibility of the nano-scale NMOSFET device fabrication using the $As_{2}^{+}$ low energy ion implantation.

• Proceedings of the KIEE Conference
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• 1993.07b
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• pp.1289-1291
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• 1993

The hydrogenation effects on characteristics of polycrystalline silicon thin film transistors(poly-Si TFT's) of which the channel length varies from $2.5{\mu}m\;to\;20{\mu}m$ and poly-Si layer thickness is 50, 100, and 150 nm was investigated. After 1 hr hydrogenation annealing by PECVD, the threshold voltage shift decreased dependent on the channel length, but channel width may not alter the threshold voltage shift. In addition to channel length, the active poly-Si layer thickness may be an important parameter on hydrogenation effects, while gate poly-Si thickness may do not influence on the characteristics of TFT's. Considering our experimental results, we propose that channel length and active poly-Si layer thickness may be a key parameters of hydrogenation of poly-Si TFT's.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.319-322
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• 1998

A 20 GHz 2-stage MMIC (Monolithic Microwave Integrated Circuits) LNA(Low Noise Amplifiers) has been designed. The pHEMT with gate length of 1.15 um has been used to provide ultra low noise and high gain amplification. Series and Shunt feedback circuits were interted to ensured high stability over frequency range of DC to 60 GHz. The size of designed MMIC LNA is 2285um x 2000um(4.57mm2). The simulated noise figure of MMIC LNA is less than 1.7 dB over frequency range of 20 GHz to 21 GHz.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.117-120
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• 2002

In this paper, we construct cryptographic accelerators using hardware Implementations of HMACS based on a hash algorithm such as MD5.It is basically a secure version of his previous algorithm, MD4 which is a little faster than MD5 The algorithm takes as Input a message of arbitrary length and produces as output a 128-blt message digest The input is processed In 512-bit blocks In this paper, new architectures, Iterative and full loop, of MD5 have been implemented using Field Programmable Gate Arrays(FPGAS). For the full-loop design, the performance Is about 500Mbps @ 100MHz

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.2
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• pp.104-115
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• 1994

This paper presents the design of a placement sysyem integrated in PCB design system. to get an optimal component positioning from part and net list. Unplaced components are placed in initial process using modified cluster development algorithm and are swapped in improvement process using the GFDR(Generalized Force Directed Relaxation) algorithm. The result is optimized in post process by component rotating or pin/gate swapping. Experimental results shwo that the placement system produces manufacturable layouts which are optimal in terms of total routing length.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.1
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• pp.91-95
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• 1990

We study the process for the reduction of bird's beak at LOCOS processing with changing the representative coefficients, oxide thickness, silicon nitride thickness, oxidetion temperature and field oxide thickness that induced the condition of bird'beak. In order to eliminate the gate oxide defects induced by selective oxidation, we used additional sacrific oxidatio. Finally we obtained the length of bird's beak to be 5000\ulcornerby SEM.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.1197-1199
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• 2009

Self-alignment for the fabrication of printed thin film transistors has become of great interest because of the resolution and registration limits of printing technologies. In this work, self-patterning and selfregistration processes are introduced, which do not need surface energy patterning and the resulting minimum gate channel length could be down to $11.2{\mu}m$ with the sheet resistance of 2.6 ${\Omega}/{\square]$ for the source and drain electrodes.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.2
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• pp.160-164
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• 2010

The radio frequency (RF) model of SOI FinFETs with gate length of 40 nm is verified by using a 3-dimensional (3-D) device simulator. This paper shows the equivalent circuit model which can be used in the circuit analysis simulator. The RMS modeling error of Y-parameter was calculated to be only 0.3 %.

• Proceedings of the KIEE Conference
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• 2002.11a
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• pp.9-12
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• 2002

NPT IGBT의 게이트 길이 최적화에 대해 수치 해석적으로 분석하였다. 게이트가 길어질 때 드리프트 영역의 전압강하는 급격히 감소하는 반면 소자 표면의 전압강하는 일정하게 증가하기 때문에 순방향 전압강하가 최소가 되는 게이트 길이를 얻을 수 있음을 보였고 시뮬레이션 결과에 부합하는 표면 전압 강하에 대한 해석적인 모델을 처음으로 제시하였으며 그 결과가 시뮬레이션과 잘 일치함을 보였다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.3
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• pp.576-581
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• 2005

In this paper. the a-Si:H TFT using ferroelectric of $SrTiO_3$ as a gate insulator is fabricated on glass. High k gate dielectric is required for on-current, threshold voltage and breakdown characteristics of TFT Dielectric characteristics of ferroelectric are superior to $SiO_2$ and $Si_3N_4$. Ferroelectric increases on-current and decreases threshold voltage of TFT and also ran improve breakdown characteristics.$SrTiO_4$ thin film is deposited by e-beam evaporation. Deposited films are annealed for 1 hour in N2 ambient at $150^{\circ}C\~600^{\circ}C$. Dielectric constant of ferroelectric is about 60-100 and breakdown field is about IMV/cm. In this paper, the TFT using ferroelectric consisted of double layer gate insulator to minimize the leakage current. a-SiN:H, a-Si:H (n-type a-Si:H) are deposited onto $SrTiO_3$ film to make MFNS(Metal/ferroelectric/a-SiN:H/a-Si:H) by PECVD. In this paper, TFR using ferroelectric has channel length of$8~20{\mu}m$ and channel width of $80~200{\mu}m$. And it shows that drain current is $3.4{\mu}A$at 20 gate voltage, $I_{on}/I_{off}$ is a ratio of $10^5\~10^8,\;and\;V_{th}$ is$4\~5\;volts$, respectively. In the case of TFT without having ferroelectric, it indicates that the drain current is $1.5{\mu}A$ at 20gate voltage and $V_{th}$ is $5\~6$ volts. If properties of the ferroelectric thin film are improved, the performance of TFT using this ferroelectric thin film can be advanced.