• Proceedings of the Korean Vacuum Society Conference
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• 2015.08a
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• pp.215.2-215.2
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• 2015

We fabricated dual active layer (DAL) thin film transistors (TFTs) with indium tin zinc oxide (ITZO) and indium gallium zinc oxide (IGZO) thin film layers using solution process. The ITZO and IGZO layer were used as the front and back channel, respectively. In order to investigate the bias stress stability of ITZO SAL (single active layer) and ITZO/IGZO DAL TFT, a gate bias stress of 10 V was applied for 1500 s under the dark condition. The SAL TFT composed of ITZO layer shows a poor positive bias stability of ${\delta}VTH$ of 13.7 V, whereas ${\delta}VTH$ of ITZO/IGZO DAL TFT was very small as 2.6 V. In order to find out the evidence of improved bias stress stability, we calculated the total trap density NT near the channel/gate insulator interface. The calculated NT of DAL and SAL TFT were $4.59{\times}10^{11}$ and $2.03{\times}10^{11}cm^{-2}$, respectively. The reason for improved bias stress stability is due to the reduction of defect sites such as pin-hole and pores in the active layer.

• 한국정보디스플레이학회:학술대회논문집
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• 2000.01a
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• pp.69-70
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• 2000

There are currently considerable interest in the applications of conjugated polymers, oligomers, and small molecules for thin-film electronic devices. Organic materials have potential advantages to be utilized as semiconductors in field-effect transistors and light-emitting diodes. In this study, pentacene thin-film transistors (TFTs) were fabricated on glass substrate. Aluminums were used for gate electrodes. Silicon dioxide was deposited as a gate insulator by PECVD and patterned by reactive ion etching (R.I.E). Gold was used for the electrodes of source and drain. The active semiconductor pentacene layer was thermally evaporated in vacuum at a pressure of about $10^{-8}$ Torr and a deposition rate $0.3{\AA}/s$. The fabricated devices exhibited the field-effect mobility as large as 0.07 $cm^2/V.s$ and on/off current ratio as larger than $10^7$.

• Proceedings of the Materials Research Society of Korea Conference
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• 2006.05a
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• pp.29.1-29.1
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• 2006

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.4
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• pp.292-297
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• 2003

We fabricated a single crystal silicon thin film transistor for active matrix organic light emitting displays(AMOLEDs) using silicon on insulator wafer (SOI wafer). Poly crystal silicon thin film transistor(poly-Si TFT) Is actively researched and developed nowsdays for a pixel switching devices of AMOLEDs. However, poly-Si TFT has some disadvantages such as high off-state leakage currents and low field-effect mobility due to a trap of grain boundary in active channel. While single crystal silicon TFT has many advantages such as high field effect mobility, low off-state leakage currents, low power consumption because of the low threshold voltage and simultaneous integration of driving ICs on a substrate. In our experiment, we compared the property of poly-Si TFT with that of SOI TFT. Poly-Si TFT exhibited a field effect mobility of 34 $\textrm{cm}^2$/Vs, an off-state leakage current of about l${\times}$10$\^$-9/ A at the gate voltage of 10 V, a subthreshold slope of 0.5 V/dec and on/off ratio of 10$\^$-4/, a threshold voltage of 7.8 V. Otherwise, single crystal silicon TFT on SOI wafer exhibited a field effect mobility of 750 $\textrm{cm}^2$/Vs, an off-state leakage current of about 1${\times}$10$\^$-10/ A at the gate voltage of 10 V, a subthreshold slope of 0.59 V/dec and on/off ratio of 10$\^$7/, a threshold voltage of 6.75 V. So, we observed that the properties of single crystal silicon TFT using SOI wafer are better than those of Poly Si TFT. For the pixel driver in AMOLEDs, the best suitable pixel driver is single crystal silicon TFT using SOI wafer.

• Korean Journal of Materials Research
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• v.28 no.12
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• pp.758-762
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• 2018

The transfer characteristics of zinc tin oxide(ZTO) on silicon dioxide($SiO_2$) thin film transistor generally depend on the electrical properties of gate insulators. $SiO_2$ thin films are prepared with argon gas flow rates of 25 sccm and 30 sccm. The rate of ionization of $SiO_2$(25 sccm) decreases more than that of $SiO_2$(30 sccm), and then the generation of electrons decreases and the conductivity of $SiO_2$(25 sccm) is low. Relatively, the conductivity of $SiO_2$(30 sccm) increases because of the high rate of ionization of argon gases. Therefore, the insulating performance of $SiO_2$(25 sccm) is superior to that of $SiO_2$(30 sccm) because of the high potential barrier of $SiO_2$(25 sccm). The $ZTO/SiO_2$ transistors are prepared to research the $CO_2$ gas sensitivity. The stability of the transistor of $ZTO/SiO_2$(25 sccm) as a high insulator is superior owing to the high potential barrier. It is confirmed that the electrical properties of the insulator in transistor devices is an important factor to detect gases.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2007.04a
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• pp.3-4
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• 2007

고분자 반도체를 이용한 유기 박막트랜지스터(OTFT) 소자 제작시 특성 향상을 위해 Self-Assemble Monolayer (SAM)을 이용한 유기 Gate 절연막과 source/drain 전극의 표면처리에 대해 설명하였다. Gate insulator의 경우 소수성 SAM이 고분자 반도체와의 상호작용으로 배열도를 향상시켜 이동도를 증가시켰으며, 전극처리의 경우 접촉저항을 낮추어 injection을 증대시키는 효과를 나타내었다. 각각의 경우 적용되는 SAM 재료와 효과를 극대화시키기 위한 처리공정 전반에 대해 설명하였다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.174-174
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• 2008

Non-volatile memories using ferroelectric-gate field-effect transistors (Fe-FETs) with a metal/ferroelectric/semiconductor gate stack (MFS-FETs) make non-destructive read operation possible. In addition, they also have features such as high switching speed, non-volatility, radiation tolerance, and high density. However, the interface reaction between ferroelectric materials and Si substrates, i.e. generation of mobile ions and short retention, make it difficult to obtain a good ferroelectric/Si interface in an MFS-FET's gate. To overcome these difficulties, Fe-FETs with a metal/ferroelectric/insulator/semiconductor gate stack (MFIS-FETs) have been proposed, where insulator as a buffer layer is inserted between ferroelectric materials and Si substrates. We prepared $SrBi_2Ta_2O_9$ (SBT) film as a ferroelectric layer and $LaZrO_x$ (LZO) film as a buffer layer on p-type (100) silicon wafer for making the MFIS-FET devices. For definition of source and drain region, phosphosilicate glass (PSG) thin film was used as a doping source of phosphorus (P). Ultimately, the n-channel ferroelectric-gate FET using the SBT/LZO/Si Structure is fabricated. To examine the ferroelectric effect of the fabricated Fe-FETs, drain current ($I_d$) versus gate voltage ($V_g$) characteristics in logarithmic scale was measured. Also, drain current ($I_d$) versus drain voltage ($V_d$) characteristics of the fabricated SBT/LZO/Si MFIS-FETs was measured according to the gate voltage variation.

• Journal of the Microelectronics and Packaging Society
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• v.16 no.2
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• pp.21-25
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• 2009

The organic-inorganic thin film transistors (OITFTs) with ZnO channel layer and the cross-linked PVP (Poly-4-vinylphenol) gate insulator were fabricated on the patterned ITO gate/glass substrate. ZnO channel layer was deposited by using atomic layer deposition (ALD). In order to improve the electrical properties, $O_2$ plasma treatment onto PVP film was introduced and investigated the effect of the plasma treatments on the electrical properties of the OITFTs. The field effect mobility and sub-threshold slope (SS) values of the OITFT decreased slightly from 0.24 to 0.16 $cm^2/V{\cdot}s$ and from 9.7 to 9.2 V/dec, respectively with increasing RF power from 30 to 50 Watt. The $I_{on/off}$ ratio was about $10^3$ for all samples with $O_2$ plasma treatment.

• Journal of the Korean Vacuum Society
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• v.20 no.5
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• pp.327-332
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• 2011

Plasma polymerized styrene (ppS) thin films were prepared on ITO coated glass substrates for a MIM (metal-insulator-metal) structure with thermally evaporated Au thin film as metal contact. Also the ppS thin films were applied as organic insulator to a MIS (metal-insulatorsemiconductor) device with thermally evaporated pentacene thin film as organic semiconductor layer. After the I-V and C-V measurements with MIM and MIS structures, the ppS revealed relatively higher dielectric constant of k=3.7 than those of the conventional poly styrene and very low leakage current density of $1{\times}10^{-8}Acm^{-2}$ at electric field strength of $1MVcm^{-1}$. The MIS structure with the ppS dielectric layer showed negligible hysteresis in C-V characteristics. It would be therefore expected that the proposed ppS could be applied as a promising dielectric/insulator to organic thin film transistors, organic memory devices, and flexible organic electronic devices.

• Journal of the Korean Applied Science and Technology
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• v.25 no.3
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• pp.388-394
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• 2008

본 논문에서는 용액 공정을 이용한 고분자 절연층을 갖는 top-gate 구조의 펜타센 박막 트랜지스터(Thin Film Transistor, TFT)의 특성을 연구하였다. Top-gate 구조의 펜타센 TFT 제작에 앞서 유기 반도체인 펜타센의 결정성 성장을 돕기 위해서 가교된 PVP (cross-linked poly(4-vinylphenol))를 유리 기판 상에 스핀 코팅을 이용하여 형성한 후, 노광 공정을 통해 니켈/은 구조를 갖는 채널 길이 $10{\mu}m$의 소오스, 드레인 전극을 형성하였다. 그리고 열 증착을 이용하여 60 nm 두께의 펜타센 층을 성막하였고, 고분자 절연체로서 PVA(polyvinyl alchol) 또는 가교된 PVA를 용액공정인 스핀 코팅을 이용하여 형성한 후 열 증착으로 알루미늄 게이트 전극을 성막하였다. 이로써 제작된 소자들의 전기적 특성을 확인한 결과 가교된 PVA를 사용한 펜타센 TFT 보다 PVA를 게이트 절연체로 사용한 소자가 전기적 특성이 우수한 것으로 관찰되었다. 이는 PVA의 가교 공정에 의한 펜타센 박막의 성능 퇴화에 기인한 것으로 사료된다. 실험 결과 $0.9{\mu}m$ 두께의 PVA 게이트 절연막을 사용한 top-gate 구조의 펜타센 TFT의 전계 효과 이동도와 문턱전압, 그리고 전류 점멸비는 각각, 약 $3.9{\times}10^{-3}\;cm^2/Vs$, -11.5 V, $3{\times}10^5$으로써 본 연구에서 제안된 소자가 용액 공정형 top-gate 유기 TFT 소자로서 우수한 성능을 나타냄을 알 수 있었다.