• 제목/요약/키워드: Gate Dielectric Film

검색결과 253건 처리시간 0.03초

Hybrid complementary circuits based on organic/inorganic flexible thin film transistors with PVP/Al2O3 gate dielectrics

  • Kim, D.I.;Seol, Y.G.;Lee, N.E.;Woo, C.H.;Ahn, C.H.;Ch, H.K.
    • 한국진공학회:학술대회논문집
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    • 한국진공학회 2011년도 제40회 동계학술대회 초록집
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    • pp.479-479
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    • 2011
  • Flexible inverters based on complementary thin-film transistor (CTFTs) are important because they have low power consumption and other advantages over single type TFT inverters. In addition, integrated CTFTs in flexible electronic circuits on low-cost, large area and mechanically flexible substrates have potentials in various applications such as radio-frequency identification tags (RFIDs), sensors, and backplanes for flexible displays. In this work, we introduce flexible complementary inverters using pentacene and amorphous indium gallium zinc oxide (IGZO) for the p-channel and n-channel, respectively. The CTFTs were fabricated on polyimide (PI) substrate. Firstly, a thin poly-4-vinyl phenol (PVP) layer was spin coated on PI substrate to make a smooth surface with rms surface roughness of 0.3 nm, which was required to grow high quality IGZO layers. Then, Ni gate electrode was deposited on the PVP layer by e-beam evaporator. 400-nm-thick PVP and 20-nm-thick ALD Al2O3 dielectric was deposited in sequence as a double gate dielectric layer for high flexibility and low leakage current. Then, IGZO and pentacene semiconductor layers were deposited by rf sputter and thermal evaporator, respectively, using shadow masks. Finally, Al and Au source/drain electrodes of 70 nm were respectively deposited on each semiconductor layer using shadow masks by thermal evaporator. Basic electrical characteristics of individual transistors and the whole CTFTs were measured by a semiconductor parameter analyzer (HP4145B, Agilent Technologies) at room temperature in the dark. Performance of those devices then was measured under static and dynamic mechanical deformation. Effects of cyclic bending were also examined. The voltage transfer characteristics (Vout- Vin) and voltage gain (-dVout/dVin) of flexible inverter circuit were analyzed and the effects of mechanical bending will be discussed in detail.

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Electrical Stress in High Permittivity TiO2 Gate Dielectric MOSFETs

  • Kim, Hyeon-Seag;S. A. Campbell;D. C. Gilmer
    • E2M - 전기 전자와 첨단 소재
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    • 제11권10호
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    • pp.94-99
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    • 1998
  • Suitable replacement materials for ultrathin SiO2 in deeply scaled MOSFETs such as lattice polarizable films, which have much higherpermittivities than SiO2, have bandgaps of only 3.0 to 4.0 eV. Due to these small bandgaps, the reliability of these films as a gate insulator is a serious concern. Ramped voltage, time dependent dielectric breakdown, and hot carrier effect measurements were done on 190 layers of TiO2 which were deposited through the metal-organic chemical vapor deposition of titanium tetrakis-isopropoxide (TTIP). Measurements of the high and low frequency capacitance indicate that virtually no interface state are created during constant current injection stress. The increase in leakage upon electrical stress suggests that uncharged, near-interface states may be created in the TiO2 film near the SiO2 interfacial layer that allow a tunneling current component at low bias.

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Low voltage operated top gated polymer thin film transistors with a high capacitance polymer dielectric

  • Jung, Soon-Won;You, In-Kyu;Noh, Yong-Young
    • 한국정보디스플레이학회:학술대회논문집
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    • 한국정보디스플레이학회 2009년도 9th International Meeting on Information Display
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    • pp.907-909
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    • 2009
  • Low voltage operated top gated polymer transistors were fabricated with a high permittivity polymer, P(VDF-TrFE) and F8T2 as a gate dielectric and semiconducting layer, respectively. The operating voltage of transistors was effectively reduced under -10 V and typical threshold voltages were as low as -1 ~ -4 V with the reasonable charge carrier mobility of $10^{-3}cm^2$/Vs for the amorphous polymer. The large hysteresis in transfer curve was improved effectively by annealing at low temperature.

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Threshold Voltage Shift in (4-pentylphenylethynyl)-dithienyl-anthracene Organic Thin-film Transistor with Self-assembled Monolayer

  • Lee, Sun-Hee;Kim, Sung-Hoon;Han, Seung-Hoon;Choi, Min-Hee;Jeong, Yong-Bin;Choo, Dong-Joon;Jang, Jin
    • 한국정보디스플레이학회:학술대회논문집
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    • 한국정보디스플레이학회 2009년도 9th International Meeting on Information Display
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    • pp.858-860
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    • 2009
  • We have applied self-assembled monolayer to make high performance and stable OTFT on the organic gate dielectric. The ${\beta}$-phenethyltrichlorosilane (SAM) was coated on the organic gate dielectric and then active layer was printed. Significant improvements in on-currents and threshold voltage shift were achieved for the SAM treated devices compared to device without SAM.

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Polylmide를 게이트 절연층으로 사용한 유기 박막 트랜지스터의 전기적 특성에 관한 연구 (A study on electrical characteristics of organic thin film transistor using polyimide for gate dielectric layer)

  • 김옥병;김윤명;김영관;김정수
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2000년도 하계학술대회 논문집 C
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    • pp.1754-1756
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    • 2000
  • Organic semiconductors based on fused-ring polycyclic aromatic hydrocarbon have great potential to be utilized as an active layer for electronic and optoelectronic devices. In this study, pentacene thin films and electrode materials were deposited by Organic Molecular Beam Deposition(OMBD) and vacuum evaporation respectively. For the gate dielectric, polyamic acid was spin-coated and cured into polyimide at 350$^{\circ}C$. Electrical characteristics of the devices were investigated, where the channel length and width was 50${\mu}m$ and 5mm. It was found that field effect mobility was 0.012$cm^{2}/Vs$, and on/off current ratio was $10^5$.

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STRUCTURAL MORPHOLOGY AND DIELECTRIC PROPERTIES OF POLYANILINE-EMERALDINE BASE AND POLY METHYL METHACRYLATE THIN FILMS PREPARED BY SPIN COATING METHOD

  • Shekar, B. Chandar;Yeon, Ji;Rhee, Shi-Woo
    • 한국정보디스플레이학회:학술대회논문집
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    • 한국정보디스플레이학회 2003년도 International Meeting on Information Display
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    • pp.1081-1084
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    • 2003
  • Structural morphology, annealing behavior and dielectric properties of polyaniline-emeraldine base (Pani-EB) and poly methyl methacrylate (PMMA) thin films prepared by spin coating technique have been studied. MIM and MISM structures were used to investigate annealing and dielectric behavior. The XRD and AFM spectrum of as grown and annealed thin films indicates the amorphous nature. The observed amorphous phase, low loss, dielectric behavior and thermal stability even at high temperatures implies the feasibility of utilizing PMMA and Pani-EB thin films as gate dielectric insulator layer in organic thin film transistors which can find application in flat panel display.

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열처리를 통한 HgSe 나노입자 기반 박막 트랜지스터의 전기적 특성 향상 (Improved Electrical Characteristics of HgSe Nanoparticle-based Thin Film Transistors by Thermal Annealing)

  • 윤정권;조경아;김상식
    • 전기전자학회논문지
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    • 제14권3호
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    • pp.219-223
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    • 2010
  • 본 연구에서는, PVA를 게이트 유전체로 이용하여 백 게이트 (back-gate) 구조의 HgSe 나노입자 박막트랜지스터를 플라스틱 기판위에 제작하였다. 제작된 박막트랜지스터는 $100^{\circ}C$ 에서 5분 동안의 열처리 과정을 통하여 이동도 $16\;cm^2$/Vs, 전류 점멸비 $10^4$의 우수한 특성을 나타내었다. 열처리에 따른 표면 거칠기의 감소가 소자의 전기적 특성향상의 원인이라는 것을 AFM 이미지를 통하여 확인 할 수 있었다. 0.6%의 strain을 기판에 인가하면서 기판의 휘어짐에 따른 전류변화를 관찰하였다.

OTFT 특성향상을 위한 이온빔 정렬처리 통한 펜타센 분자의 비등방 정렬 (Organization of pentacene molecules using an ion-beam treatment for organic thin film transistors)

  • 김영환;김병용;김대현;한정민;서대식
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2009년도 하계학술대회 논문집
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    • pp.116-116
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    • 2009
  • This paper focuses on improving organic thin film transistor (OTFT) characteristics by controlling the self-organization of pentacene molecules with an alignable high-dielectric-constant film. The process, based on the growth of pentacene film through high-vacuum sublimation, is a method of self-organization using ion-beam (IB) bombardment of the $HfO_2/Al_2O_3$ surface used as the gate dielectric layer. X-ray photoelectron spectroscopy indicates that the IB raises the rate of the structural anisotropy of the $HfO_2/Al_2O_3$ film, and X-ray diffraction patterns show the possibility of increasing the anisotropy to create the self-organization of pentacene molecules in the first polarized monolayer.

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고유전율 AIN 절연층을 사용한 비휘발성 강유전체 메모리용 MFIS 구조의 제작 및 특성 (Fabrications and Properties of MFIS Structures using high Dielectric AIN Insulating Layers for Nonvolatile Ferroelectric Memory)

  • 정순원;김광희;구경완
    • 대한전자공학회논문지SD
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    • 제38권11호
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    • pp.765-770
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    • 2001
  • 고온 급속 열처리시킨 LiNbO₃/AIN/Si(100) 구조를 이용하여 MFIS 소자를 제작하고, 비휘발성 메모리 동작 가능성을 확인하였다. 고유전율 AIN 박막 위에 Pt 전극을 증착시켜 제작한 MIS 구조에서 측정한 1MHz C-V 특성곡선에서는 히스테리시스가 전혀 없고 양호한 계면특성을 보였으며, 축적 영역으로부터 산출한 비유전율 값은 약 8 이었다. Pt/LiNbO₃/AIN/Si(100) 구조에서 측정한 1MHz C-V 특성의 축적영역에서 산출한 LiNbO₃ 박막의 비유전율 값은 약 23 이었으며, ±5 V의 바이어스 범위 내에서의 메모리 윈도우는 약 1.2 V이었다. 이 MFIS 구조에서의 게이트 누설전류밀도는 ±500 kV/cm의 전계 범위 내에서 10/sup -9/ A/㎠ 범위를 유지하였다. 500 kHz의 바이폴러 펄스를 인가하면서 측정한 피로특성은 10/sup 11/ cycle 까지 초기값을 거의 유지하는 우수한 특성을 보였다.

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Channel과 gate 구조에 따른 산화물 박막트랜지스터의 전기적 특성 연구 (Effect of Channel and Gate Structures on Electrical Characteristics of Oxide Thin-Film Transistors)

  • 공희성;조경아;김재범;임준형;김상식
    • 전기전자학회논문지
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    • 제26권3호
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    • pp.500-505
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    • 2022
  • 본 연구에서는 새로운 구조의 dual gate tri-layer split channel 박막트랜지스터를 제작하였다. 전류 구동 능력을 향상시키기 위해 액티브 층의 양쪽에 게이트를 형성하였고 전하이동도를 증가시키기 위하여 액티브 층에서 채널이 형성되는 구간인 첫번째 층과 세번째 층에 전도성이 높은 ITO 층을 배치하였다. 추가적으로 분할 채널을 이용하여 채널의 series 저항을 낮추면서 분할한 채널의 측면에서도 accumulation을 유도하여 전하이동도를 향상시켰다. 기존의 single gate a-ITGZO 박막트랜지스터가 15 cm2/Vs의 전하이동도를 가지는 반면 dual gate tri-layer split channel 박막트랜지스터는 134 cm2/Vs의 높은 전하이동도를 가졌다.