• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.89-89
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• 2011

a-GIZO(비정질 Ga-In-Zn-O)박막은 유연하며 광학적으로 투명하고 높은 전자의 이동도를 갖는 반도체적 특성을 갖기 때문에 차세대 display분야에서 TFT(Thin-Film-Transistor)의 high speed active-matrix layer로써 각광을 받고 있다. 이 물질의 표면은 환경 및 표면처리에 매우 민감하며 [1,2], 이 표면에 metal이 증착되는 경우에도, 선행 연구에 의하면, 다양한 chemical state가 나타남을 알 수 있었다. 이것은 metal의 증착에 따라 metal과 a-GIZO 사이의 contact 저항이 달라짐을 의미한다. 우리는 a-GIZO 박막 위에 Au를 단계적으로 증착시키면서, Au coverage 증가에 따른 core-level과 valence에서의 x-ray photoelectron spectra의 변화를 살펴봄으로써 a-GIZO박막과 Au의 계면에서 일어나는 chemical state의 변화를 알 수 있었다. 특히, Au deposition의 전 처리과정으로써 Ne ion sputtering을 두 단계로 다르게 하여 a-GIZO의 표면환경에 따른 Au 증착의 영향을 살펴보았다.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.08a
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• pp.252-252
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• 2011

최근 주목받고 있는 amorphous gallium-indium-zinc-oxide (a-GIZO) thin film transistors (TFTs)는 수소가 첨가된 비정질 실리콘 TFT에 비해 높은 이동도와 뛰어난 전기적, 광학적 특성에 의해 큰 주목을 받고 있다. 또한 넓은 밴드갭을 가지므로 가시광 영역에서 투명한 특성을 보이고, 플라스틱 기판 위에서 구부러지는 성질에 의해 플랫 패널 디스플레이나 능동 유기 발광소자 (AM-OLED), 투명 디스플레이에 응용되고 있다. 뿐만 아니라, 일반적인 Poly-Si TFT는 자체적으로 가지는 결정성에 의해 대면적화 시 균일성이 좋지 못하지만 GIZO는 비정질상 이기 때문에 백플레인의 대면적화에 유리하다는 장점이 있다. 이러한 TFT를 제작하기 전, 전기적 특성에 대한 정보를 얻거나 예측하는 것이 중요한데, 이에 따라 고안된 구조가 바로 metal point contact FET (pseudo FET)이다. pseudo FET은 소스/드레인 전극을 따로 증착할 필요 없이 채널을 증착한 후, 프로브 탐침을 채널의 표면에 적당한 압력으로 접촉시켜 전하를 공급하는 소스와 드레인처럼 동작시킬 수 있다. 따라서 소스/드레인을 증착하거나 lithography와 같은 추가적인 공정을 요구하지 않아 소자의 특성을 보다 간단하고 수월하게 분석할 수 있다는 장점이 있다. 본 연구에서는 p-type 기판위에 100nm의 oxidation SiO2를 게이트 절연막으로 사용하는 a-GIZO pseudo FET를 제작하였다. 소자 제작 후, 열처리 온도에 따른 전기적 특성을 분석하였고, 열처리 조건은 30분간 N2 분위기에서 실시하였다. 열처리 후 전기적 특성 분성 결과, 450oC에서 가장 낮은 subthreshold swing 값과 게이트 전압의 더블 스윕 후 문턱 전압의 변화가 거의 없음을 확인하였다.

• Journal of Sensor Science and Technology
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• v.22 no.2
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• pp.105-110
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• 2013

We fabricated an a-IGZO thin film transistor (TFT) with AZO/Ag/AZO transparent multilayer source/drain contacts by rf magnetron sputtering. a-IGZO TFT with AZO/Ag/AZO multilayer S/D electrodes (W/L = 400/50 ${\mu}m$) showed a subs-threshold swing of 3.78 V/dec, a minimum off-current of $10^{-12}$ A, a threshold voltage of 0.41 V, a field effect mobility of $10.86cm^2/Vs$, and an on/off ratio of $9{\times}10^9$. From the ultraviolet photoemission spectroscopy, it was revealed that the enhanced electrical performance resulted from the lowering of the Schottky barrier between a-IGZO and Ag due to the insertion of an AZO layer and thus the AZO/Ag/AZO multilayer would be very appropriate for a promising S/D contact material for the fabrication of high performance TFTs.

• Journal of the Korean institute of surface engineering
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• v.44 no.4
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• pp.144-148
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• 2011

$Ga_2O_3$ doped $SnO_2$ thin films were grown by using pulsed laser deposition (PLD) technique on glass substrate. The optical and electrical properties of these films were investigated for different doping concentrations, oxygen partial pressures, substrate temperatures, and film thickness. The films were deposited at different substrate temperatures (room temperature to $600^{\circ}C$). The best opto-electrical properties is shown by the film deposited at substrate temperature of $300^{\circ}C$ with oxygen partial pressure of 80 m Torr and the gallium concentration of 2 wt%. The as obtained lowest resistivity is $9.57{\times}10^{-3}\;{\Omega}cm$ with the average transmission of 80% in the visible region and an optical band gap (indirect allowed) of 4.26 eV.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.462-462
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• 2013

Gallium Oxide (Ga2O3) has been widely investigated for the optoelectronic applications due to its wide bandgap and the optical transparency. Recently, with the development of fabrication techniques in nanometer scale semiconductor materials, there have been an increasing number of extensive reports on the synthesis and characterization of Ga2O3 nano-structures such as nano-wires, nanobelts, and nano-dots. In contrast to typical vaporliquid-solid growth mode with metal catalysts to synthesis 1-dimensional nano-wires, there are several difficulties in fabricating the nanostructures by using sputtering techniques. This is attributed to the fact that relatively low growth temperatures and higher growth rate compared with chemical vapor deposition method. In this study, Ga2O3 chestnut burr were synthesized by using radio-frequency magnetron sputtering method. In contrast to typical sputtering method with sintered ceramic target, a Ga2O3 powder (99.99% purity) was used as a sputtering target. Several samples were prepared with varying the growth parameters, especially he growth time and the growth temperature to investigate the growth mechanism. Samples were characterized by using XRD, SEM, and PL measurements. In this presentation, the details of fabrication process and physical properties of Ga2O3 nano chestnut burr will be reported.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.5
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• pp.373-376
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• 2009

In this paper we report upon an investigation into the effect of DC bias voltage on the electrical and optical properties of Gallium doped zinc oxide (GZO) film. GZO films were deposited on glass substrate without substrate temperature by RF magnetron sputtering from a ZnO target mixed with 5 wt% $Ga_{2}O_{3}$. we investigated sample properties of bias voltage change in 0 to -60 V. We were able to achieve as low as $5.89{\times}10^{-4}{\Omega}cm$ and transmittance over 88 %. without substrate heating.

• ETRI Journal
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• v.38 no.1
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• pp.133-140
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• 2016

This paper presents a method of parasitic inductance reduction for high-speed switching and high-efficiency operation of a cascode structure with a low-voltage enhancement-mode silicon (Si) metal-oxide-semiconductor field-effect transistor (MOSFET) and a high-voltage depletion-mode gallium nitride (GaN) fielde-ffect transistor (FET). The method is proposed to add a bonding wire interconnected between the source electrode of the Si MOSFET and the gate electrode of the GaN FET in a conventional cascode structure package to reduce the most critical inductance, which provides the major switching loss for a high switching speed and high efficiency. From the measured results of the proposed and conventional GaN cascode FETs, the rising and falling times of the proposed GaN cascode FET were up to 3.4% and 8.0% faster than those of the conventional GaN cascode FET, respectively, under measurement conditions of 30 V and 5 A. During the rising and falling times, the energy losses of the proposed GaN cascode FET were up to 0.3% and 6.7% lower than those of the conventional GaN cascode FET, respectively.

• ETRI Journal
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• v.35 no.4
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• pp.610-616
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• 2013

This paper proposes a transparent logic circuit for radio frequency identification (RFID) tags in amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistor (TFT) technology. The RFID logic circuit generates 16-bit code programmed in read-only memory. All circuits are implemented in a pseudo-CMOS logic style using transparent a-IGZO TFTs. The transmittance degradation due to the transparent RFID logic chip is 2.5% to 8% in a 300-nm to 800-nm wavelength. The RFID logic chip generates Manchester-encoded 16-bit data with a 3.2-kHz clock frequency and consumes 170 ${\mu}W$ at $V_{DD}=6$ V. It employs 222 transistors and occupies a chip area of 5.85 $mm^2$.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.169-170
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• 2007

In this paper we report upon an investigation into the effect of sputter pressure and RF power on the electrical properties of Gallium doped zinc oxide (GZO) film. GZO films were deposited on glass substrate without substrate temperature by RF magnetron sputtering from a ZnO target mixed with 5 wt% $Ga_2O_3$. Argon gas pressure and RF power were in the range of 1~11 mTorr, and 50~100 W, respectively. However, the resistivity of the film was strongly influenced by the sputter pressure and RF power. We were able to achieve as low as $1.5{\times}10^{-3}\;{\Omega}cm$, without substrate temperature.

• Korean Journal of Materials Research
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• v.16 no.10
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• pp.652-655
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• 2006

A direct wafer bonding process necessary for GaAs-on-insulator (GOI) fabrication with high thermal annealing temperatures was studied by using PECVD oxides between gallium arsenide and silicon wafers. In order to apply some uniform pressure on initially-bonded wafer pairs, a graphite sample holder was used for wafer bonding. Also, a tool for measuring the tensile forces was fabricated to measure the wafer bonding strengths of both initially-bonded and thermally-annealed samples. GaAs/$SiO_2$/Si wafers with 0.5-$\mu$m-thick PECVD oxides were annealed from $100^{\circ}C\;to\;600^{\circ}C$. Maximum bonding strengths of about 84 N were obtained in the annealing temperature range of $400{\sim}500^{\circ}C$. The bonded wafers were not separated up to $600^{\circ}C$. As a result, the GOI wafers with high annealing temperatures were demonstrated for the first time.