• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.1
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• pp.76-80
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• 2011

This paper has proposed a 3~5 GHz low-power and wideband LNA(Low Noise Amplifier), which has been implemented in a 0.18-${\mu}m$ CMOS technology. The proposed LNA has basically the noise-cancelling topology to achieve a balun-function, wideband input matching, and relative low noise figure. In addition, it has utilized a 2nd-order LC-band-pass filter(BPF) as its output load to achieve higher power gain and lower noise figure with the lowest dc power consumption among previously reported works. The proposed amplifier consumes only 3.94 mA from a 1.8 V supply voltage. The simulation results show a power gain of more than +17 dB, a noise figure of less than +4 dB, and an input IP3 of -15.5 dBm.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.3
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• pp.282-288
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• 2014

In this paper, we have analyzed and designed a digital RF receiver based on the optimization of the dynamic range parameter to secure the wideband characteristics and linearity of digital radar receivers. To improve the wideband characteristics and dynamic range, a low noise amplifier is matching design with a noise source to minimize the noise figure in 1 GHz bandwidth and we improved the linearity of RF-receiver by securing the conversion gain characteristics of receiver through the design of active mixer. RF receiver is designed to give gain 63 dB, noise figure 1.2 dB and dynamic range of RF receiver has 75.8 dB in a wide band of 8.8~9.8 GHz. It is shown to be applicable to X-band digital radar receiver.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.12
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• pp.1445-1454
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• 2008

In this paper, small UWB antenna with band-stop function for mobile handsets is proposed. A gap between radiator and under and side ground is adjusted for small size and broadband. A radiator is folded to the back side of PCB for miniaturization and tapered feeding structure is used to enhance matching characteristic. A antenna clearance has a size of $14{\times}14\;mm^2$ and a size of radiator is $10{\times}7\;mm^2$. It covers all UWB band from 3.15 GHz to 4.75 GHz and from 7.2 GHz to 10.2 GHz for VSWR<2 and has band stop characteristic at 5.8 GHz. A maximum gain is measured as 5.85 GHz. In case conventional handset case is considered, it also covers all UWB and a maximum gain is measured from -2 dBi to -2 dBi.

• Journal of Advanced Navigation Technology
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• v.9 no.2
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• pp.103-109
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• 2005

This paper presents the design of a broadband hybrid mixer using dual-gate FET topology with a low-pass filter which improves return loss of output to isolate RF and LO signal. The low-pass filter shows the isolation with RF and LO signal of better than 40 dBc from 1.5 GHz to 5.5 GHz. The dual-gate mixer which has been designed by using cascade topology operates when the lower FET is biased in linear region and the upper FET is in saturation region. The input matching circuit has been designed to have conversion gain from 1.5 GHz to 5.5 GHz. The designed mixer with low-pass filter shows the conversion gain of better than 7 dB from 1.5 GHz to 5.5 GHz at the low LO power level of 0 dBm with the fixed IF frequency of 21.4 MHz.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.583-585
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• 2012

In this paper, we introduce a design method for a broadband planar quasi-Yagi antenna (QYA) for terrestrial digital television (DTV) receiving. The coplanar strip line feeding the driver dipole is connected to a microstrip line and is terminated by short circuit. By appending a wide strip-type director at a location close to the driver dipole, a broadband impedance matching and a gain characteristics in a high frequency region are obtained. The gain characteristics in a low frequency region are improved by adding a reflector formed by a truncated ground plane. To reduce the antenna size, the strip-type dipole and reflector are modified to half bowtie (V)-shaped elements. The effects of various parameters on the antenna characteristics are examined. An antenna, as an design example for the proposed antenna, is designed for the operation in the frequency band of 470-806 MHz for terrestrial DTV. The optimized antenna is fabricated on an FR4 substrate and tested experimentally to verify the results of this study.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.12
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• pp.1069-1074
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• 2016

This paper presents a V-band two-stage power amplifier integrated circuit using TSMC 65 nm CMOS process. The simple input, output, and inter-stage matching networks based on passive components are integrated. By compensating for power gain characteristics using a pre-distortion technique, the linearity of the power amplifier was improved. The implemented two-stage power amplifier showed a power gain of 10.4 dB, a saturated output power of 9.7 dBm, and an efficiency of 20.8 % with a supply voltage of 1 V at the frequency band of 58.8 GHz.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.5C
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• pp.469-477
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• 2007

Most multimedia source coders exhibit unequal bit error sensitivity. Efficient transmission system design should therefore incorporate the use of matching unequal error protection (UEP). In this paper, we present and evaluate a flexible space-time coding system with unequal error protection. Multiple transmit and receive antennas and bit-interleaved coded modulation techniques are used combined with rate compatible punctured convolutional codes. A near optimum iterative receiver is employed with a multiple-in multiple-out inverse mapper and a MAP decoder as component decoders. We illustrate how the UEP system gain can be achieved either as a power or bandwidth gain compared to the equal error protection system (EEP) for the identical source and equal overall quality for both the UEP and EEP systems. An example with two/three transmit and two receive antennas using BPSK modulation is given for the block fading channel.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.1
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• pp.100-108
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• 2014

Low noise amplifier (LNA) is an integral component of RF receiver and frequently required to operate at wide frequency bands for various wireless system applications. For wideband operation, important performance metrics such as voltage gain, return loss, noise figure and linearity have been carefully investigated and characterized for the proposed LNA. An inductive shunt feedback configuration is successfully employed in the input stage of the proposed LNA which incorporates cascaded networks with a peaking inductor in the buffer stage. Design equations for obtaining low and high impedance-matching frequencies are easily derived, leading to a relatively simple method for circuit implementation. Careful theoretical analysis explains that input impedance can be described in the form of second-order frequency response, where poles and zeros are characterized and utilized for realizing the wideband response. Linearity is significantly improved because the inductor located between the gate and the drain decreases the third-order harmonics at the output. Fabricated in $0.18{\mu}m$ CMOS process, the chip area of this wideband LNA is $0.202mm^2$, including pads. Measurement results illustrate that the input return loss shows less than -7 dB, voltage gain greater than 8 dB, and a little high noise figure around 6-8 dB over 1.5 - 13 GHz. In addition, good linearity (IIP3) of 2.5 dBm is achieved at 8 GHz and 14 mA of current is consumed from a 1.8 V supply.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.6
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• pp.646-652
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• 2014

This paper presents a design and fabrication of Ku-band power amplifier using Gallium Nitride High Electron Mobility Transistor (GaN HEMT) die. In order to fabricate the low-cost Ku-band power amplifier, a Printed Circuit Board(PCB) was used for input/output matching circuits instead of manufacturing process to use an expensive substrate. The measured output power is 42.6 dBm, the drain efficiency is 37.7 % and the linear gain is 7.9 dB under pulse operation at the frequency of 14.8 GHz. Under the continuous wave(CW) test, the output power is 39.8 dBm, the drain efficiency is 24.1 % and the linear gain is 7.2 dB.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.22 no.6
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• pp.141-147
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• 2008

This paper describes the design of frequency down converting Mixer in the receiver to use compound semiconductor and CMOS product process. The basic theory and structure of frequency down converting Mixer is surveyed, and we design mixer circuit with active balun which use the compound semiconductor and CMOS process. This mixer convert a single ended signal to differential signal at input port of RF and LO instead of matching circuit to get dual band balanced mixer structure and characteristic broadband. This designed mixer has a conversion gain $-1{\sim}-6[dB]$ at $2{\sim}6[GHz]$ bandwidths. However, the simulation of the designed mixer with active balun has the result of a 7[dB] conversion gain for -2[dBm] LO input power and -10[dBm] input P1[dB] at 5.8[GHz].