• Proceedings of the KIEE Conference
• /
• 1991.07a
• /
• pp.720-725
• /
• 1991

In this thesis, the lead-lag compensator is designed to improve output characteristics of flyback zero voltage switching quasi-resonant converters. The switch and the diode are assumed ideally. And the SMPS is modelled by state equations with four operation modes. And the model for controller design is also achived by using a state space averaging method, which is continuous time average of state variables every period. The lag, the lead and the lead-lag compensator is designed the SMPS respectively. The time domain analysis and the frequency domain analysis are done for each compensated circuit. It is possible increasing the phase margin and improving the transient response by the compensators. The phase lag compensator has small overshoot comparatively. But the bandwidth is narrower than the others, so it has longest settling time. For the phase lead compensator, the response come to steady-state within short period. But the overshoot is the largest due to its large peak gain. Finally, the phase lead-lag compensator has medium characteristics in the overshoot and the settling time.

• Journal of Institute of Control, Robotics and Systems
• /
• v.9 no.2
• /
• pp.117-123
• /
• 2003

Rotational machines such as optical disk drives, hard disk drives, and so on are subject to periodic disturbances caused by their mechanical characteristics. In the meanwhile, it is well known that repetitive control rejects periodic disturbance effectively. This paper presents a practical application of repetitive control to the track-following servo of an optical disk drive. The repetitive control system is composed of two repetitive controllers which compensate for periodic disturbances generated by track geometry and eccentric rotation of disk and a feedback controller stabilizing the feedback loop. A robust stability for all plant uncertainties is proved using linear matrix inequalities (LMIs). In the controller design, a weighting function is introduced for the feedback controller to ensure a minimum loop gain and a sufficient phase margin. The repetitive controllers and the feedback controller are designed by solving an optimization problem which can consider the robust stability condition and the system performance. The developed repetitive control system is implemented in the digital control system with a 16-bit fixed-point digital signal processor (DSP). Through simulation and experiment. The feasibility of the proposed repetitive control system is verified.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
• /
• 2001.11a
• /
• pp.65-72
• /
• 2001

Power system stabilizer act efficiently to damp the electromechanical oscillations in interconnected power systems. This paper presents an algorithm for the optimal parameter selection of a power system stabilizer in two-area power systems with a series HVDC link. This method is one of the classical techniques by allocating properly pole-zero positions to fit as closely as desired the ideal phase lead between the voltage reference and the generator electrical power and by changing the gain to produce a necessary damping torque over the matched frequency range. Control of HVDC converter and inverter are used a constant current loop. Proper parameters of PI controllers are obtain based on the Root-locus technique in other to have sufficient speed and stability margin to cope with charging reference values and disturbance. The small signal stability arid transient stability studies using the PSS parameters obtained from this method show that a natural oscillation frequency of the studycase system is adequately damped. Also the simulation results using the HVDC converter and inverter parameters obtained from this proposed method show proper current control characteristics. The simulation used in the paper was performed by the Power System Toolbox software program based on MATLAB.

• Transactions of the Korean Society for Noise and Vibration Engineering
• /
• v.16 no.12 s.117
• /
• pp.1252-1261
• /
• 2006

This paper summarizes theoretical work on the multichannel decentralized feedback control of sound radiation from aircraft trim panels using piezoceramic actuators. The aircraft trim panels are generally honeycomb structures designed to meet the design requirement of low weight and high stiffness. They are resiliently-mounted to the fuselage for the passive reduction of noise transmission. It is motivated by the localization of reduction in vibration of single channel active trim panels. 12-channel decentralized feedback control systems are investigated in terms of the reduction of noise and vibration for three configurations of sensor actuator pairs. Local coupling of the closely-spaced sensor and actuator pairs was modeled using single degree of freedom systems. The multichannel control system is characterized using the state-space model. For the stability point of view, the relative stability or robustness is evaluated by comparing the real part of eigenvalues of the system matrix for the three configurations. The control performance is also evaluated and compared for the three configurations. It is found that the multichannel system can lead to the globalization of the reduction in vibration and radiated noise. It does not appear to yield a significant improvement in the vibration because of decreased gain margin. However, the reduction in the radiated noise is remarkably improved due to the variation of the vibration pattern with the actuation configurations.

• Proceedings of the KIEE Conference
• /
• 2005.07d
• /
• pp.2552-2554
• /
• 2005

제어기 설계에서 이득여유와 위상여유는 견실성 및 안정도 판별의 중요한 척도로 사용되며, 그 중 위상여유는 시스템의 성능지수와 관련된다. 이와 같은 이유로 이득여유와 위상여유의 안정도를 고려한 제어기의 설계방법이 연구되어지고 있다. 근래 Weng Khuen Ho와 Chang Chieh Hang이 제안한 설계방법은 복잡한 계산을 필요로 하는 arctan 함수를 1차 선형함수로 근사화 하여 복잡도를 감소시키면서도 원하는 이득여유와 위상여유를 만족시키는 제어기의 파라미터를 찾았다. 하지만 이 방법은 실제의 arctan 함수를 사용하는 것이 아니라 근사화된 수식을 사용함으로써 오차가 수반되어 원하는 설계조건을 만족 하지 못한다. 따라서 본 논문은 이러한 오차를 최소화하기 위해서 최적화 알고리즘을 이용한 이득여유와 위상여유를 보상하는 PID 제어기를 설계하였다.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.7 no.1
• /
• pp.20-27
• /
• 2007

An analytic design guide was formulated for the design of 3-stage CMOS OP amp with the nested Gm-C(NGCC) frequency compensation. The proposed design guide generates straight-forwardly the design parameters such as the W/L ratio and current of each transistor from the given design specifications, such as, gain-bandwidth, phase margin, the ratio of compensation capacitance to load capacitance. The applications of this design guide to the two cases of 10pF and 100pF load capacitances, shows that the designed OP amp work with a reasonable performance in both cases, for the range of compensation capacitance from 10% to 100% of load capacitance.

• Journal of IKEEE
• /
• v.18 no.1
• /
• pp.37-44
• /
• 2014

In this paper we present an LDO based on an error amplifier. The designed error amplifier has a gain of 89.93dB at low frequencies. This amplifier's Bandwidth is 50.8MHz and its phase margin is $59.2^{\circ}C$. Also we proposed a BGR. This BGR has a low output variation with temperature and its PSRR at 1 KHz is -71.5dB. For a temperature variation from $-40^{\circ}C$ to $125^{\circ}C$ we have just 9.4mV variation in 3.3V LDO output. Also it is stable for a wide range of output load currents [0-200mA] and a $1{\mu}F$ output capacitor and its line regulation and especially load regulation is very small comparing other papers. The PSRR of proposed LDO is -61.16dB at 1 KHz. Also we designed it for several output voltages by using a ladder of resistors, transmission gates and a decoder. Low power consumption is the other superiority of this LDO which is just 1.55mW in full load. The circuit was designed in $0.35{\mu}m$ CMOS process.

• Proceedings of the IEEK Conference
• /
• 2008.06a
• /
• pp.565-566
• /
• 2008

The high efficiency power management IC(PMIC) for Moblie application is proposed in this paper. PMIC is controlled with PWM control method in order to have high power efficiency at high current level. The saw-tooth generator is made to have 1.2 MHz oscillation frequency and full range of output swing from ground to supply voltage(VDD:3.3V). The comparator is designed with two stage OP amplifier. And the error amplifier has 70dB DC gain and $64^{\circ}$ phase margin. DC-DC converter, based on Voltage-mode PWM control circuits, achieved the high efficiency near 95% at 100mA output current. DC-DC converter is designed with LDO in stand-by mode which fewer than 1mA for high efficiency.

• Aerospace Engineering and Technology
• /
• v.2 no.1
• /
• pp.108-116
• /
• 2003

This research presents the design and analysis of PCDU(Power Control & Distribution Unit) of communication satellite. The PCDU of a spacecraft must provide adequate power to each subsystem and payload during mission life, and it also needs high reliability and performance in space environment. A control circuit of the PCDU include bus sensing and filter circuits, error signal amplification circuit, error compensation circuit of SAS(Shunt Assembly Switch) and BPC(Battery Power Converter). The phase margin and DC gain for the designed circuits are analyzed through the frequency response characteristics of the compensated control circuit. And also the transfer function of the battery power converter circuit are discussed at the battery CCCM(Charge Continuous Conduction Mode) and battery C/DCCM(Continuous/Discontinuous Conduction Mode).

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.13 no.6
• /
• pp.622-634
• /
• 2013

The circuit level implementation of nanoscale Insulated Shallow Extension Silicon On Nothing (ISE-SON) MOSFET has been investigated and compared with the other conventional devices i.e. Insulated Shallow Extension (ISE) and Silicon On Nothing (SON) using the ATLAS 3D device simulator. It can be observed that ISE-SON based inverter shows better performance in terms of Voltage Transfer Characteristics, noise margin, switching current, inverter gain and propagation delay. The reliability issues of the various devices in terms of supply voltage, temperature and channel length variation has also been studied in the present work. Logic circuits (such as NAND and NOR gate) and ring oscillator are also implemented using different architectures to illustrate the capabilities of ISE-SON architecture for high speed logic circuits as compared to other devices. Results also illustrates that ISE-SON is much more temperature resistant than SON and ISE MOSFET. Hence, ISE-SON enables more aggressive device scaling for low-voltage applications.