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Institute of Korean Electrical and Electronics Engineers (한국전기전자학회)
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A High Current Efficiency CMOS LDO Regulator with Low Power Consumption and Small Output Voltage Variation

  • Rikan, Behnam Samadpoor (College of Information and Communication Engineering, Sungkyunkwan University) ;
  • Abbasizadeh, Hamed (College of Information and Communication Engineering, Sungkyunkwan University) ;
  • Kang, Ji-Hun (College of Information and Communication Engineering, Sungkyunkwan University) ;
  • Lee, Kang-Yoon (College of Information and Communication Engineering, Sungkyunkwan University)
  • Received : 2014.01.15
  • Accepted : 2014.02.25
  • Published : 2014.03.31
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Abstract

In this paper we present an LDO based on an error amplifier. The designed error amplifier has a gain of 89.93dB at low frequencies. This amplifier's Bandwidth is 50.8MHz and its phase margin is $59.2^{\circ}C$. Also we proposed a BGR. This BGR has a low output variation with temperature and its PSRR at 1 KHz is -71.5dB. For a temperature variation from $-40^{\circ}C$ to $125^{\circ}C$ we have just 9.4mV variation in 3.3V LDO output. Also it is stable for a wide range of output load currents [0-200mA] and a $1{\mu}F$ output capacitor and its line regulation and especially load regulation is very small comparing other papers. The PSRR of proposed LDO is -61.16dB at 1 KHz. Also we designed it for several output voltages by using a ladder of resistors, transmission gates and a decoder. Low power consumption is the other superiority of this LDO which is just 1.55mW in full load. The circuit was designed in $0.35{\mu}m$ CMOS process.

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References

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