• 반도체디스플레이기술학회지
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• 제18권4호
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• pp.138-142
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• 2019

As the NAND flash memory goes to 3D vertical Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) structure, the lateral charge migration can be critical in the reliability performance. Even more, with miniaturization of flash memory cell device, just a little movement of trapped charge can cause reliability problems. In this paper, we propose a method of predicting the trapped charge profile in the retention mode. Charge diffusivity in the charge trapping layer (Si₃N₄) was extracted experimentally, and the effect on the trapped charge profile was demonstrated by the simulation and experiment.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2019년도 전력전자학술대회
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• pp.271-272
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• 2019

본 논문은 친환경 전기차용에 적용되는 있는 고밀도 LDC(Low-Voltage DC-DC Converter) 전력변환장치의 PCB구조와 스위칭소자에 따른 PCB의 발열특성을 해석한다. 전력변환장치 PCB사이에 알루미늄 플레이트를 적용하여 다면 방열경로를 통한 PCB방열특성을 비교하고, 또한 기존 Si-FET와 낮은 온 상태 도통저항을 가지는 GaN-FET 반도체디바이스를 적용한 전력변환장치의 PCB 방열특성을 시뮬레이션을 통해 비교 및 검토하였다.

• 한국전기전자재료학회논문지
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• 제37권2호
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• pp.133-140
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• 2024

This study offers a comprehensive evaluation of the role and impact of advanced power semiconductors in solar module systems. Focusing on silicon carbide (SiC) and gallium nitride (GaN) materials, it highlights their superiority over traditional silicon in enhancing system efficiency and reliability. The research underscores the growing industry demand for high-performance semiconductors, driven by global sustainable energy goals. This shift is crucial for overcoming the limitations of conventional solar technology, paving the way for more efficient, economically viable, and environmentally sustainable solar energy solutions. The findings suggest significant potential for these advanced materials in shaping the future of solar power technology.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 추계학술대회 논문집 Vol.19
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• pp.15-16
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• 2006

The thermal stability of nickel silicide with compressively and tensilely stressed nitride capping layer has been investigated in this study. The Ni (10 nm) and Ni/Co/TiN (7/3/25 nm) structures were deposited on the p-type Si substrate. The stressed capping layer was deposited using plasma enhanced chemical vapor deposition (PECVD) after silicide formation by one-step rapid thermal process (RTP) at $500^{\circ}C$ for 30 sec. It was found that the thermal stability of nickel silicide depends on the stress induced by the nitride capping layer. In the case of Ni (10 nm) structure, the high compressive sample shows the best thermal stability, whereas in the case of Ni/Co/TiN (7/3/25 nm) structure, the high compressive sample shows the worst thermal stability.

• 한국전기전자재료학회논문지
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• 제32권3호
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• pp.201-206
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• 2019

This report constitutes the first demonstration in Korea of single-crystal lateral gallium oxide ($Ga_2O_3$) as a metal-oxide-semiconductor field-effect-transistor (MOSFET), with a breakdown voltage in excess of 480 V. A Si-doped channel layer was grown on a Fe-doped semi-insulating ${\beta}-Ga_2O_3$ (010) substrate by molecular beam epitaxy. The single-crystal substrate was grown by the edge-defined film-fed growth method and wafered to a size of $10{\times}15mm^2$. Although we fabricated several types of power devices using the same process, we only report the characterization of a finger-type MOSFET with a gate length ($L_g$) of $2{\mu}m$ and a gate-drain spacing ($L_{gd}$) of $5{\mu}m$. The MOSFET showed a favorable drain current modulation according to the gate voltage swing. A complete drain current pinch-off feature was also obtained for $V_{gs}<-6V$, and the three-terminal off-state breakdown voltage was over 482 V in a $L_{gd}=5{\mu}m$ device measured in Fluorinert ambient at $V_{gs}=-10V$. A low drain leakage current of 4.7 nA at the off-state led to a high on/off drain current ratio of approximately $5.3{\times}10^5$. These device characteristics indicate the promising potential of $Ga_2O_3$-based electrical devices for next-generation high-power device applications, such as electrical autonomous vehicles, railroads, photovoltaics, renewable energy, and industry.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제43회 하계 정기 학술대회 초록집
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• pp.86-86
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• 2012

The new approaches for silicon solar cell of new concept have been actively conducted. Especially, solar cells with wire array structured radial p-n junctions has attracted considerable attention due to the unique advantages of orthogonalizing the direction of light absorption and charge separation while allowing for improved light scattering and trapping. One-dimenstional semiconductor nano/micro structures should be fabricated for radial p-n junction solar cell. Most of silicon wire and/or pillar arrays have been fabricated by vapour-liquid-solid (VLS) growth because of its simple and cheap process. In the case of the VLS method has some weak points, that is, the incorporation of heavy metal catalysts into the growing silicon wire, the high temperature procedure. We have tried new approaches; one is electrochemical etching, the other is noble metal catalytic etching method to overcome those problems. In this talk, the silicon pillar formation will be characterized by investigating the parameters of the electrochemical etching process such as HF concentration ratio of electrolyte, current density, back contact material, temperature of the solution, and large pre-pattern size and pitch. In the noble metal catalytic etching processes, the effect of solution composition and thickness of metal catalyst on the etching rate and morphologies of silicon was investigated. Finally, radial p-n junction wire arrays were fabricated by spin on doping (phosphor), starting from chemical etched p-Si wire arrays. In/Ga eutectic metal was used for contact metal. The energy conversion efficiency of radial p-n junction solar cell is discussed.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권1호
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• pp.53-60
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• 2014

Different kinds of post-deposition annealing (PDA) by a rapid thermal process (RTP) are used to enhance the field-effect passivation of $Al_2O_3$ film in crystal Si solar cells. To characterize the effects of PDA on $Al_2O_3$ and the interface, metal-insulator semiconductor (MIS) devices were fabricated. The effects of PDA were characterized as functions of RTP temperature from $400{\sim}700^{\circ}C$ and RTP time from 30~120 s. A high temperature PDA can retard the passivation of thin $Al_2O_3$ film in c-Si solar cells. PDA by RTP at $400^{\circ}C$ results in better passivation than a PDA at $400^{\circ}C$ in forming gas ($H_2$ 4% in $N_2$) for 30 minutes. A high thermal budget causes blistering on $Al_2O_3$ film, which degrades its thermal stability and effective lifetime. It is related to the film structure, deposition temperature, thickness of the film, and annealing temperature. RTP shows the possibility of being applied to the PDA of $Al_2O_3$ film. Optimal PDA conditions should be studied for specific $Al_2O_3$ films, considering blistering.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
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• pp.10-10
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• 2008

Silicide is inevitable for CMOSFETs to reduce RC delay by reducing the sheet resistance of gate and source/drain regions. Ni-silicide is a promising material which can be used for the 65nm CMOS technologies. Ni-silicide was proposed in order to make up for the weak points of Co-silicide and Ti-silicide, such as the high consumption of silicon and the line width limitation. Low resistivity NiSi can be formed at low temperature ($\sim500^{\circ}C$) with only one-step heat treat. Ni silicide also has less dependence of sheet resistance on line width and less consumption of silicon because of low resistivity NiSi phase. However, the low thermal stability of the Ni-silicide is a major problem for the post process implementation, such as metalization or ILD(inter layer dielectric) process, that is, it is crucial to prevent both the agglomeration of mono-silicide and its transformation into $NiSi_2$. To solve the thermal immune problem of Ni-silicide, various studies, such as capping layer and inter layer, have been worked. In this paper, the Ni-silicide utilizing Pd stacked layer (Pd/Ni/TiN) was studied for highly thermal immune nano-scale CMOSFETs technology. The proposed structure was compared with NiITiN structure and showed much better thermal stability than Ni/TiN.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2016년도 제50회 동계 정기학술대회 초록집
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• pp.256-256
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• 2016

기존의 디스플레이 기슬은 마스크를 통해 특정 부분에만 유기재료를 증착시키는 방법을 사용하였으나, 기판의 크기가 커짐에 따라 공정조건에 제약이 발생하였다. 이를 해결하기 위해 최근 용액 공정에 대한 연구가 활발히 진행되고 있다. 용액 공정은 기존 진공 증착 방식과 비교하였을 때 상온, 대기압에서 증착이 가능하며 경제적이고, 대면적 균일 증착에 유리하다는 장점이 있다. 반면, 용액 공정으로 제작한 소자는 시간이 지남에 따라 점차 전기적 특성이 변하는 aging effect를 보인다. Aging effect는 용액에 포함된 C기와 OH기 기반의 불순물의 영향으로 시간의 경과에 따라서 문턱전압, subthreshold swing 및 mobility 등의 전기적 특성이 변하는 현상으로 고품질의 박막을 형성하기 위해서는 고온의 열처리가 필요하다. 지금까지 고품질 박막 형성을 위한 열처리는 퍼니스 (furnace) 장비에서 주로 이루어졌는데, 시간이 오래 걸리고, 상대적으로 고온 공정이기 때문에 유리, 종이, 플라스틱과 같은 다양한 기판에 적용하기 어렵다는 단점이 있다. 따라서, 본 연구에서는 $100^{\circ}C$ 이하의 저온에서도 열처리가 가능한 microwave irradiation (MWI) 방법을 이용하여 solution-processed InGaZnO TFT를 제작하였고, 기존의 열처리 방식인 furnace로 열처리한 TFT 소자와 aging effect를 비교하였다. 먼저, solution-processed IGZO TFT를 제작하기 위해 p type Si 기판을 열산화시켜서 100 nm의 SiO2 게이트 산화막을 성장시켰고, 스핀코팅 방법으로 a-IGZO 채널층을 형성하였다. 증착후 열처리를 위하여 1000 W의 마이크로웨이브 출력으로 15분간 MWI를 실시하여 a-IGZO TFT를 제작하였고, 비교를 위하여 furnace N2 gas 분위기에서 $600^{\circ}C$로 30분간 열처리한 TFT를 준비하였다. 제작된 직후의 TFT 특성을 평가한 결과, MWI 열처리한 소자가 퍼니스 열처리한 소자보다 높은 이동도, 낮은 subthreshold swing (SS)과 히스테리시스 전압을 가지는 것을 확인하였다. 한편, aging effect를 평가하기 위하여 제작 후에 30일 동안의 특성변화를 측정한 결과, MWI 열처리 소자는 30일 동안 문턱치 전압(VTH)의 변화량 ${\Delta}VTH=3.18[V]$ 변화되었지만, furnace 열처리 소자는 ${\Delta}VTH=8.56[V]$로 큰 변화가 있었다. 다음으로 SS의 변화량은 MWI 열처리 소자가 ${\Delta}SS=106.85[mV/dec]$인 반면에 퍼니스 열처리 소자는 ${\Delta}SS=299.2[mV/dec]$이었다. 그리고 전하 트래핑에 의해서 발생하는 게이트 히스테리시스 전압의 변화량은 MWI 열처리 소자에서 ${\Delta}V=0.5[V]$이었지만, 퍼니스 열처리 소자에서 ${\Delta}V=5.8[V]$의 큰 수치를 보였다. 결과적으로 MWI 열처리 방식이 퍼니스 열처리 방식보다 소자의 성능이 우수할 뿐만 아니라 aging effect가 개선된 것을 확인할 수 있었고 차세대 디스플레이 공정에 있어서 전기적, 화학적 특성을 개선하는데 기여할 것으로 기대된다.

• 한국결정성장학회지
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• 제14권6호
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• pp.244-252
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• 2004

$CuISe_2$ 단결정 박막은 수평 전기로에서 합성한 $CuInSe_2$ 다결정을 증발원으로하여, hot wall epitaxy(HWE) 방법으로 증발원과 기판(반절연성-GaAs(100))의 온도를 각각 $620^{\circ}C$, $410^{\circ}C$로 고정하여 단결정 박막을 성장하였다. 이때 단결정 박막의 결정성은 광발광 스펙트럼과 이중결정 선 요동곡선(DCRC) 으로 부터 구하였다. Hall 효과는 van der Pauw 방법에 의해 측정되었으며, 293K에서 운반자 농도와 이동도는 각각 $9.62\times10^{16}/\textrm{cm}^3$, 296 $\textrm{cm}^2$/Vㆍs 였다. $CuAlSe_2$/Si(Semi-Insulated) GaAs(100) 단결정 박막의 광흡수와 광전류 spectra를 293k에서 10K까지 측정하였다. 광흡수 스펙트럼으로부터 band gap $E_g$(T)는 Varshni 공식에 따라 계산한 결과 1.1851 eV-($8.99\times10^{-4} eV/K)T^2$/(T+153k)였다. 광전류 스펙트럼으로 부터 Hamilton matrix(Hopfield quasicubic mode)법으로 계산한 결과 crystal field splitting Δcr값이 0.0087eV이며 spin-orbit Δso값은 0.2329 eV임을 확인하였다. 10K일 때 광전류 봉우리들은 n = 1일때 $A_1-, B_1$-와 $C_1$-exciton봉우리임을 알았다.