• Title/Summary/Keyword: GaAs FET

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Single-bias GaAs MMIC single-ended mixer for cellular phone application (Cellular phone용 단일 전원 MMIC single-ended 주파수 혼합기 개발)

  • 강현일;이상은;오재응;오승건;곽명현;마동성
    • Journal of the Korean Institute of Telematics and Electronics D
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    • v.34D no.10
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    • pp.14-23
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    • 1997
  • An MMIC downconverting mixer for cellular phone application has been successfully developed using an MMIC process including $1 \mu\textrm{m}$ ion implanted gaAs MESFET and passive lumped elements consisting of spiral inductor, $Si_3N_4$ MIM capacitor and NiCr resistor. The configuration of the mixer presented in this paper is single-ended dual-gate FET mixer with common-source self-bias circuits for single power supply operation. The dimension of the fabricated circuit is $1.4 mm \times 1.03 mm $ including all input matching circuits and a mixing circuit. The conversion gian and noise figure of the mixer at LO powr of 0 dBm are 5.5dB and 19dB, respectively. The two-tone IM3 characteristics are also measured, showing -60dBc at RF power of -30dBm. Allisolations between each port show better than 20dB.

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A GaAs MMIC Single-Balanced Upconverting Mixer With Built-in Active Balun for PCS Applications (PCS 용 MMIC Single-blanced upconverting 주파수 혼합기 설계 및 제작)

  • 강현일;이원상;정기웅;오재응
    • Journal of the Korean Institute of Telematics and Electronics D
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    • v.35D no.4
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    • pp.1-8
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    • 1998
  • An MMIC single-balanced upconverting mixer for PCS application has been successfully developed using an MMIC process employed by 1 .mu. ion implanted GaAs MESFET and passive lumped elements consisting of spiral inductor, Si3N4 MIM capacitors and NiCr resistors. The configuration of the mixer presented in this paper is two balanced cascode FET mixers with common-source self-bias circuits for single power supply operation. The dimension of the fabricated circuit including two active baluns intermodulation characteristic with two-tone excitation are also measured, showing -28.17 dBc at IF power of -30 dBm.

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고집적 GaAs 디지틀 집접회로 제작을 위한 Self-aligned MESFET 공정

  • Yang, Jeon-Uk;Shim, Kyu-Hwan;Choi, Young-Kyu;Cho, Lack-Hie;Park, Chul-Soon;Lee, Keong-Ho;Lee, Jin-Hee;Cho, Kyoung-Ik;Kang, Jin-Yeong;Lee, Yong-Tak
    • ETRI Journal
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    • v.13 no.4
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    • pp.35-41
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    • 1991
  • 저전력 고집적 GaAs 디지틀 IC에 적합한 기본 논리회로인 DCFL (Direct Coupled FET Logic) 을 구현하기 위한 소자로 WSi게이트 MESFET 공정을 연구하였으며, 이와 함께 TiPtAu 게이트 소자를 제작하였다. MESFET 의 제작은 내열성게이트를 이용한 자기정렬 이온주입 공정을 사용하였으며 주입된 Si 이온은 급속열처리 방법으로 활성화하였다. 또한 제작공정중 저항성 접촉의 형성은 절연막을 이용한 리프트 - 오프 공정을 이용하였다. 제작된 WSi게이트 MESFET은 $1\mum$ 게이트인 경우 222mS/mm의 트랜스컨덕턴스를 나타내어 우수한 동작특성과 집적회로 공정의 적합성을 보였으며 이와 동등한 공정조건으로 제작된 TiPtAu 게이트 MESFET 은 2" 기판 내에서 84mV의 임계전압 변화를 나타내었다.

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A 3.3V, 68% power added efficieny, GaAs power MESFET for mobile digital hand-held phone (3.3V 동작 68% 효율, 디지털 휴대전화기용 고효율 GaAs MESFET 전력소자 특성)

  • 이종남;김해천;문재경;이재진;박형무
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.32A no.6
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    • pp.41-50
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    • 1995
  • A state-of-the-arts GaAs power metal semiconductor field effect transistor (MESFET) for 3.3V operation digital hand-held phone at 900 MHz has been developed for the first time, The FET was fabricated using a low-high doped structures grown by molecular beam epitaxy (MBE). The fabricated MESFETs with a gate width of 16 mm and a gate length of 0.8 .mu.m shows a saturated drain current (Idss) of 4.2A and a transconductance (Gm) of around 1700mS at a gate bias of -2.1V, corresponding to 10% Idss. The gate-to-drain breakdown voltage is measured to be 28 V. The rf characteristics of the MESFET tested at a drain bias of 3.3 V and a frequencyof 900 MHz are the output power of 32.3 dBm, the power added efficiency of 68%, and the third-ordr intercept point of 49.5 dBm. The power MESFET developed in this work is expected to be useful as a power amplifying device for digital hand-held phone because the high linear gain can deliver a high power added efficiency in the linear operation region of output power and the high third-order intercept point can reduce the third-order inter modulation.

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Development of the Low Noise Amplifier for Cellular CDMA Using a Resistive Decoupling Circuit (저항 결합회로를 이용한 Cellular CDMA용 저잡음 증폭기의 구현)

  • 전중성;김동일
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.2 no.4
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    • pp.635-641
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    • 1998
  • This paper presents development of a small size LNA operating at 824 ∼ 849 MHz used for a receiver of a CELLULAR CDMA Base station and a transponder. Using resistive decoupling circuits, a signal at low frequency is dissipated by a resistor. This design method increases the stability of the LNA and is suitable for input stage matching. The LNA consists of low noise GaAs FET ATF-10136 and internally matched VNA-25. The LNA is fabricated with both the RF circuit and the self-bias circuits in aluminum housing. As a result, the characteristics of the LNA implemented here shows above 35dB in gain and below 0.9dB in noise figure, 18.6dBm P1dB power, a typical two tone IM3, -31.17dB with single carrier backed off 10dB from P1dB.

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Design and Implementation of Broadband RF Amplifier for Microwave Receiver (마이크로웨이브 수신기용 광대역 RF 증폭기 설계 및 제작)

  • Kim, Jae-Hyun;Yoon, In-Seop;Go, Min-Ho;Park, Hyo-Dal
    • The Journal of the Korea institute of electronic communication sciences
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    • v.10 no.6
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    • pp.665-670
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    • 2015
  • In this paper, We proposed a broadband RF amplifier for Microwave band receiver. We also proposed a broadband RF amplifier, designed by using EM simulation for reliable amplification of the received signal. Connected to a source terminal to via, it minimizes those which are the active elements of source-side oscillation as the operating element in an ideal GND, and a constant gain characteristic in a broadband. The goal of this was to obtain stable amplification characteristics. For implementing this architecture, we designed the broadband(500 MHz ~ 7 GHz) RF amplifier by using commercial GaAs FET, which operate on 720 MHz, 4,595 MHz, and 6,035 MHz by impedance matching. The voltage gain is 10.635 dB ~ 14.407 dB(737.5 MHz ~ 6.0575 GHz), P1dB is 20 dBc of band(1st harmonic/2nd harmonic).

A Study on the Fabrication of the Low Noise Amplifier Using Resistive Decoupling circuit and Series feedback Method (저항결합 회로와 직렬 피드백 기법을 이용한 저잡음 증폭기의 구현에 관한 연구)

  • 유치환;전중성;황재현;김하근;김동일
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2000.10a
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    • pp.190-195
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    • 2000
  • This paper presents the fabrication of the LNA which is operating at 2.13∼2.16 GHz for IMT-2000 lot-end receiver using series feedback and resistive decoupling circuit. Series feedback added to the source lead of a transistor keep the low noise characteristics and drop the input reflection coefficient of amplifier simultaneously. Also, it increases the stability of the LNA. Resistive decoupling circuit is suitable for input stage matching because a signal at low frequency is dissipated by a resistor in the matching network The amplifier consist of GaAs FET ATF-10136 for low noise stage and VNA-25 which is internally matched MMIC for high gain stage. The amplifier is fabricated with both the RF circuits and self bias circuit on the Teflon substrate with 3.5 permittivity. The measured results of the LNA which is fabricated using above design technique are presented more than 30 dB in gain P$\_$ldB/ 17 dB and less than 0.7 dB in noise figure, 1.5 in input$.$output SWR(Standing Wave Ratio).

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A Study on the Fabrication of 1W Power Amplifier for IMT2000 Repeater Using Nonlinear Analysis (비선형 해석법을 이용한 IMT2000 중계기용 1W 전력증폭기 제작 연구)

  • 전광일
    • Journal of the Institute of Electronics Engineers of Korea TE
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    • v.37 no.2
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    • pp.83-90
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    • 2000
  • A simple low-cost and small size 1.88-198 GHz Band RF power amplifier module is developed for IMT2000 repeater. The power amplifier consists of two stage amplifiers that the first stage amplifier is drive amplifier using discrete type P-HEMT (ATF-34143, 800 micron gate width, Agilent Technologies) and the second is power amplifier with 300Bm 1dB gain compression point using GaAs FET(EFA240D-SOT89, 2400 micron gate width, Excelics Semiconductor). this power amplifier module feature a 29.5dBm 1dB gain compression point, 29.5dB gain, 42dBm 3rd order intercept point(OIP3) and -10dB/-l2dB input/output return loss over the 1880-1980 MHz. This PA module is fully integrated using MIC technology into a small size and design by full nonlinear design technologies. The dimensions of this PA module are 42(L) $\times$ 34(W) mm.

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Miniaturized DBS Downconverter MMIC Showing a Low Noise and Low Power Dissipation Characteristic (저잡음ㆍ저소비전력 특성을 가지는 위성방송 수신용 초소형 다운컨버터 MMIC)

  • Yun, Young
    • Journal of Navigation and Port Research
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    • v.27 no.4
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    • pp.443-447
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    • 2003
  • In this work. using 0.2 GaAs modulation doped FET(MODFET), a high performance DBS downconverter MMIC was developed for direct broadcasting satellite (DBS) application. Without LNA, the downconverter MMIC showed a very low noise of 4.8 dB, which is lower by 3 dB than conventional ones. A low LO power of -10 dBm was required for the normal DBS operation of the downconverter MMIC. which reduced the power consumption via a removal of LO amplifier on MMIC. It required only a low power consumption of 175 mW, which is lower than 70 percent of conventional ones. The LO leakage power at IF output was suppressed to a lower level than 30 dBm, which removes a bulky LO rejection filter on a board. The fabricated chip, which include a mixer, If amplifiers. LO rejection filter, and active balun, exhibited a small size of $0.84{\times}0.9\textrm{mm}^2$.

LNA Design Uses Active and Passive Biasing Circuit to Achieve Simultaneous Low Input VSWR and Low Noise (낮은 입력 정재파비와 잡음을 갖는 수동 및 능동 바이어스를 사용한 저잡음증폭기에 관한 연구)

  • Jeon, Joong-Sung
    • Journal of Advanced Marine Engineering and Technology
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    • v.32 no.8
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    • pp.1263-1268
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    • 2008
  • In this paper, the low noise power amplifier for GaAs FET ATF-10136 is designed and fabricated with active bias circuit and self bias circuit. To supply most suitable voltage and current, active bias circuit is designed. Active biasing offers the advantage that variations in the pinch-off voltage($V_p$) and saturated drain current($I_{DSS}$) will not necessitate a change in either the source or drain resistor value for a given bias condition. The active bias network automatically sets a gate-source voltage($V_{gs}$) for the desired drain voltage and drain current. Using resistive decoupling circuits, a signal at low frequency is dissipated by a resistor. This design method increases the stability of the LNA, suitable for input stage matching and gate source bias. The LNA is fabricated on FR-4 substrate with active and self bias circuit, and integrated in aluminum housing. As a results, the characteristics of the active and self bias circuit LNA implemented more than 13 dB and 14 dB in gain, lower than 1 dB and 1.1 dB in noise figure, 1.7 and 1.8 input VSWR at normalized frequency $1.4{\sim}1.6$, respectively.