• The Journal of the Korea institute of electronic communication sciences
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• v.12 no.5
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• pp.817-828
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• 2017

It is very hard to find the system which processes single 10Gbps stream, and the related application is also rare. But in the field of science such as physics and astronomy, these high speed systems have been widely used and now more upgraded performance is expected. For this reason, high speed network based storage which captures and records 10Gbps level of packets was developed for the support of small astronomical company in KASI. But for the use of the system in research, system performance should be not only evaluated but also optimized. In this paper, we first implement system environment for the performance evaluation and discuss the experiment procedure and solution to acquire numerical results.

• International Commerce and Information Review
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• v.12 no.1
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• pp.99-121
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• 2010

This paper reviews the categories and properties of risk measures, analyzes the classes and structural equations of volatility forecasting models, and presents the practical methodologies and their expansion methods of estimating and forecasting the volatilities of exchange rates using Excel spreadsheet modeling. We apply the GARCH(1,1) model to the Korean won(KRW) denominated daily and monthly exchange rates of USD, JPY, EUR, GBP, CAD and CNY during the periods from January 4, 1998 to December 31, 2009, make the estimates of long-run variances in the returns of exchange rate calculated as the step-by-step change rate, and test the adequacy of estimated GARCH(1,1) model using the Box-Pierce-Ljung statistics Q and chi-square test-statistics. We demonstrate the adequacy of GARCH(1,1) model in estimating and forecasting the volatility of exchange rates in the monthly series except the semi-variance GARCH(1,1) applied to KRW/JPY100 rate. But we reject the adequacy of GARCH(1,1) model in estimating and forecasting the volatility of exchange rates in the daily series because of the very high Box-Pierce-Ljung statistics in the respective time lags resulting to the self-autocorrelation. In conclusion, the GARCH(1,1) model provides for the easy and helpful tools to forecast the exchange rate volatilities and may become the powerful methodology to overcome the application difficulties with the spreadsheet modeling.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.05a
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• pp.394-397
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• 2003

In this paper, we describe the implementation of high performance buffer manager that is used in an advanced input-queued switch fabric. The designed buffer manager provides wire-speed cell/packet routing with low cost and tolerates the transmission pipeline latency of request and grant data. The buffer manager is implemented in a FPGA chip and supports the speed of OC-48c, 2.5Gbps per port.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.2
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• pp.355-362
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• 2013

A hardware implementation of phase calculator for extracting 3D depth image from TOF(Time-Of-Flight) sensor is described. The designed phase calculator, which adopts a pipelined architecture to improve throughput, performs arctangent operation using vectoring mode of CORDIC algorithm. Fixed-point MATLAB modeling and simulations are carried out to determine the optimized bit-widths and number of iteration. The designed phase calculator is verified by FPGA-in-the-loop verification using MATLAB/Simulink, and synthesized with a TSMC 0.18-${\mu}m$ CMOS cell library. It has 16,000 gates and the estimated throughput is about 9.6 Gbps at 200Mhz@1.8V.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.36 no.8
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• pp.816-823
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• 2008

This paper describes the test results of developed high speed data processing unit using Xilinx GTP(Multi-Gigabit-Transceiver) interface and DDR-2 memory. The high speed data processing unit receives input data from packet generator at 1.25Gbps and transmits stored data to the data receiving system at 700Mbps. Therefore, DDR-2 memory controller and Xilinx GTP interface are implemented by FPGA instead of CPU to process high speed data directly.

• The Journal of Asian Finance, Economics and Business
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• v.5 no.2
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• pp.5-14
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• 2018

This study is motivated based on concern from some renowned scholars and central bankers whom have raised the issue of the sustainability of the International Monetary System (IMS). Using the panel data set of four major international currencies, USD, JPY, EUR and GBP from 1973 to 2013 with Pooled Mean Group (PMG) estimator, to re-examine whether Triffin dilemma still exists through investigating the relationship between the reserve share, current account balance and real effective exchange rate. The evidence from the result indicates that Triffin dilemma exists only in the long run, and shows that in the long-run, current account balance is proportionate to the increased real effective exchange rate while varies inversely with the reserve shares. However, the estimation for the short-run is not significant to prove the existence of Triffin dilemma. In addition, we investigated the non-dollar panel sample and found that the international monetary system still suffers from Triffin dilemma even without the dollar. To overcome Triffin dilemma, immediate step such as having currency swap mechanism is recommended. In medium term, a multi-polar Monetary System is suggested, and in the longer time, a supranational currency will be used to replace all the currencies in the world.

• Journal of Advanced Navigation Technology
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• v.13 no.1
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• pp.27-33
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• 2009

New optical transmission link techniques improving performance of WDM channels, each channel have bit rate of 40 Gbps, are proposed. The proposed optical link configuration consist of optical phase conjugator (OPC) placed at middle of total transmission length, and dispersion management (DM) as a role of compensating dispersion cumulated in transmission line. It is confirmed that Q-factor of total channels are improved by combining OPC and DM in optical transmission link as a result of following fact; DM not only mitigate the cumulated dispersion in total transmission line but also help OPC to compensate optical nonlinearities. And, it is confirmed that the improvement of Q-factor of overall WDM channels depends on net residual dispersion (NRD) of optical link.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.2
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• pp.291-297
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• 1997

A 2.5 Gbp$\times$8 channel WDM signal was transmitted using read-deployed 123 km optical cable around Daejon area. An error free transmission was achieved with $10^{-10}$ criterion, but the receiver sensitivity varied depending on channel, and some channel showed BER floor. The reans was forud to be in reflection points, and the effects of multiple reflections on the ultra high bit transmission was found to be inreflection points, and the effects of multiple reflections on the ultra high bit transmission was analyzed in this paper.

• The Bulletin of The Korean Astronomical Society
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• v.39 no.2
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• pp.105.2-105.2
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• 2014

Mark6는 최대 16Gbps의 데이터 입출력을 지원하는 차세대 기록 시스템으로서 올 하반기 내에 KVN의 관측 연구에 활용되기 위해 현재 기록 실험이 진행 중에 있다. VDIF(VLBI Data Interchage Format) 기반의 Mark6가 KVN 각 사이트에서 실제 관측에 활용되기 위해서는 FILA10G, VOA(VSI Optical Adapter) 등의 VSI-VDIF 컨버터가 수반되어야 하며 샘플러, DAS(Data Acquisition System) 등 내부적으로도 많은 시스템 변화가 필요하다. 본 발표에서는 기본 사양, 동작 원리 등 Mark6에 대한 간단한 소개를 시작으로 데이터 기록 실험 결과에 대해 설명하고자 한다. 나아가 이를 기반으로 향후 KVN의 광대역 관측 수행을 위한 Mark6의 활용 방안에 대해 살펴보고자 한다.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.791-794
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• 2003

The increasing computational capability of processors is driving the need for high bandwidth links to communicate and store the information that is processed. Such links are often an important part of multi processor interconnection, processor-to-memory interfaces and Serial-network interfaces. This paper describes a 0.11-${\mu}{\textrm}{m}$ CMOS 4 Gbp s/pin 3-Level transceiver using RSL/(Rambus Signaling Logic) for high bandwidth. This system which uses a high-gain windowed integrating receiver with wide common-mode range which was designed in order to improve SNR when operating with the smaller input overdrive of 3-Level. For multi-gigabit/second application, the data rate is limited by Inter-Symbol Interference (ISI) caused by low pass effects of channel, process-limited on-chip clock frequency, and serial link distance. In order to detect the transmited 4Gbps/pin with 3-Level data sucessfully ,the receiver is designed using 3-stage sense amplifier. The proposed transceiver employes multi-level signaling (3-Level Pulse Amplitude Modulation) using clock multi phase, double data rate and Prbs patten generator. The transceiver shows data rate of 3.2 ~ 4.0 Gbps/pin with a 1GHz internal clock.