• Transactions of the Korean Society of Automotive Engineers
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• v.14 no.4
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• pp.192-198
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• 2006

The real-time simulator of a turning-type sluice gate actuated by the hydraulic cylinders is developed using a PC and a visual C++ program language. The real-time simulator receives the directional control valve signal selected by the operator using the mouse, updates the state variables of the turning-type sluice gate system responding to the control signal, and draws the moving figures of the sluice gate, cylinder, reserved water every drawing time on the PC monitor. Also, the operator can observe the sluice gate angle, cylinder force, cylinder pressures, and hydraulic power representing the operation of sluice gate system through the PC monitor every drawing time. The simulator can be a very useful tool to design and improve the turning-type sluice gate system.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.49 no.9
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• pp.523-526
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• 2000

A dual gate trench emitter IGBT structure is proposed and studied numerically using the device simulator MEDICI. The on-state forward voltage drop latch-up current density turn-off time and breakdown voltage of the proposed structure are compared with those of the conventional DMOS-IGBT and trench gate IGBT structures. The proposed structure forms an additional channel and increases collector current level resulting in reduction of on -state forward voltage drop. In addition the trench emitter increases latch-up current density by 148% in comparison with that for the conventional DMOS-IGBT and by 83% compared with that for the trench gate IGBT without degradation in breakdown voltage when the half trench gate width(Tgw) and trench emitter depth(Ted) are fixed at $1.5\mum\; and\; 2\mum$, respectively

• The Journal of Korean Association of Computer Education
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• v.11 no.2
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• pp.65-78
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• 2008

Many digital logic circuit simulators have been developed for the education on the experiments of digital logic circuits for college or high school students. But the existing simulators have some constraints on the number of inputs of gate, on the display of gate and wire states, and on the number of logic diagrams to be simulated. 1n this paper, we propose a simulator XSIM(eXpandable digital logic circuit SIMulator) which mitigates the constraints and allows multiple diagrams for large scale logics. It is expected that the multiple diagrams on large logics are helpful for team-teaching in school.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.11a
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• pp.498-501
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• 2002

In this paper, we designed double gate(DG) MOSFET structure which has main gate(MG) and two side gates(SG). We have simulated using TCAD simulator. DG MOSFET have the main gate length of nm and the side gate length of 70nm. Then, we have investigated the pinch-off characteristics, drain voltage is changed from 0V to 1.5V at VMG=1.5V and VSG=3.0V. In spite of the LMG is very small, we have obtained a very good pinch-off characteristics. Therefore, we know that the DG structure is very useful at nino scale.

• Proceedings of the KIEE Conference
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• 1993.07b
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• pp.1292-1294
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• 1993

This paper proposes a new structure of polycrystalline silicon(poly-Si) thin film transistor(TFT) having a thick gate-oxide below the gate edge. The new structure is fabricated by the gate re-oxidation in wet ambient. It is shown that the thick gate-oxide below the gate edge is effective in reducing the leakage current and the gate-drain overlap capacitance. We have simulated this device by using the SSUPREM4 process simulator and the SPISCES-2B device simulator. As a simulation result it is found that the new structure provides a low tentage current less than 0.2 pA and achieves a on/off ratio as high as $5{\times}10^7$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.7
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• pp.1074-1078
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• 2002

In this paper, we designed double gate(DG) MOSFET structure which has main gate(MG) and two side gates(SG). We have simulated using TCAD simulator U .WOSFET have the main gate length of %m and the side gate length of 70nm. Then, u'e have investigated the pinch-off characteristics, drain voltage is changed from 0V to 1.5V at VMG=1.5V and VSG=3.0V. In spite of the LMG is very small, we have obtained a very good pinch-off characteristics. Therefore, we know that the DG structure is very useful at nano scale.

• Journal of Power Electronics
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• v.16 no.2
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• pp.553-563
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• 2016

This paper presents a digital hardware implementation of a real-time simulator for a multiphase drive using a field-programmable gate array (FPGA) device. The simulator was developed with a modular and hierarchical design using very high-speed integrated circuit hardware description language (VHDL). Hence, this simulator is flexible and portable. A state-space representation model suitable for FPGA implementations was proposed for a dual three-phase induction machine (DTPIM). The simulator also models a two-level 12-pulse insulated-gate bipolar transistor (IGBT)-based voltage-source converter (VSC), a pulse-width modulation scheme, and a measurement system. Real-time simulation outputs (stator currents and rotor speed) were validated under steady-state and transient conditions using as reference an experimental test bench based on a DTPIM with 15 kW-rated power. The accuracy of the proposed digital hardware implementation was evaluated according to the simulation and experimental results. Finally, statistical performance parameters were provided to analyze the efficiency of the proposed DTPIM hardware implementation method.

• Proceedings of the KIEE Conference
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• 1987.07b
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• pp.1577-1580
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• 1987

This paper proposes a gate and functional level logic simulator which can be run on XENIX O.S. The simulator has hierarchical structure including Hardware Description Language compiler, Waveform Description Language compiler, and Simulation Command Language compiler. The Hardware Description Language compiler generates data structure composed of gate structure, wire structure, condition structure, and event structure. Simulation algorithm is composed of selective trace and event-driven methods. To improve simulation speed, Cross Referenced Linked List Structure ia defined in building the data structure of circuits.

• Journal of Sensor Science and Technology
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• v.23 no.4
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• pp.284-289
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• 2014

In this paper, modeling of a gate/body-tied (GBT) PMOSFET photodetector with built-in transfer gate is performed. It can control the photocurrent with a high-sensitivity. The GBT photodetector is a hybrid device consisted of a MOSFET, a lateral BJT, and a vertical BJT. This device allows for amplifying the photocurrent gain by $10^3$ due to the GBT structure. However, the operating parameters of this photodetector, including its photocurrent and transfer characteristics, were not known because modeling has not yet been performed. The sophisticated model of GBT photodetector using a process simulator is not compatible with circuit simulator. For this reason, we have performed SPICE modeling of the photodetector with reduced complexity using Cadence's Spectre program. The proposed modeling has been demonstrated by measuring fabricated chip by using 0.35 im 2-poly 4-metal standard CMOS technology.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.53-56
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• 2002

We have developed a Monte Carlo (MC) simulator for electron beam lithography in multi-layer resists and multi-layer substrates in order to fabricate and develop high-speed PHEMT devices for millimeter- wave applications. For the deposited energy calculation to multi-layer resists by electron beam in MC simulation, we modeled newly for multi-layer resists and heterogeneous multi-layer substrates. Using this model, we simulated T-gate or r-gate fabrication process in PHEMT device and showed our results with SEM observations.