• The Transactions of the Korean Institute of Power Electronics
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• v.26 no.5
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• pp.325-333
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• 2021

A 3 kW grid-tied PV inverter with Gallium nitride high-electron mobility transistor (GaN HEMT) for domestic commercialization was developed using boost converter and full-bridge inverter with LCL filter topology. Recently, many GaN HEMTs are manufactured as surface mount packages because of their lower parasitic inductance characteristic than standard TO (transistor outline) packages. A surface mount packaged GaN HEMT releases heat through either top or bottom cooling method. IGOT60R070D1 is selected as a key power semiconductor because it has a top cooling method and fairly low thermal resistances from junction to ambient. Its characteristics allow the design of a 3 kW inverter without forced convection, thereby providing great advantages in terms of easy maintenance and high reliability. 1EDF5673K is selected as a gate driver because its driving current and negative voltage output characteristics are highly optimized for IGOT60R070D1. An LCL filter with passive damping resistor is applied to attenuate the switching frequency harmonics to the grid-tied operation. The designed LCL filter parameters are validated with PSIM simulation. A prototype of 3 kW PV inverter with GaN HEMT is constructed to verify the performance of the power conversion system. It achieved high power density of 614 W/L and peak power efficiency of 99% for the boost converter and inverter.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.10a
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• pp.219-220
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• 2016

A power management system (PMS) has been an important part in a ship integrated control system. To evaluate a PMS for a liquefied natural gas carrier (LNGC), this research proposes a real-time hardware-in-the-loop simulation (HILS), which is composed of major component models such as turbine generator, diesel generator, governor, circuit breaker, and 3-phase loads on MATLAB/Simulink. In addition, FPGA based control console and main switchboard (MSBD) are constructed in order to develop an efficient control and a similar real environment in an LNGC PMS. A comparative study on the performance evaluation of PMS functions is conducted using two test cases for sharing electric power to consumers in an LNGC. The result shows that the proposed system has a high verification capability for the operating function and failure insertion evaluation as a PMS simulator.

• Journal of the Korean Physical Society
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• v.73 no.11
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• pp.1764-1773
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• 2018

A-PET is a quad-head PET scanner developed for use in small-animal imaging. The dimensions of its volumetric field of view (FOV) are $46.1{\times}46.1{\times}46.1mm^3$ and the gap between the detector modules has been minimized in order to provide a highly sensitive system. However, such a small FOV together with the quad-head geometry causes image quality degradation. The main factor related to image degradation for the quad-head PET is the mispositioning of events caused by the penetration effect in the detector. In this paper, we propose a precise method for modelling the system at the high spatial resolution of the A-PET using a LOR (line of response) based ML-EM (maximum likelihood expectation maximization) that allows for penetration effects. The proposed system model provides the detection probability of every possible ray-path via crystal sampling methods. For the ray-path sampling, the sub-LORs are defined by connecting the sampling points of the crystal pair. We incorporate the detection probability of each sub-LOR into the model by calculating the penetration effect. For comparison, we used a standard LOR-based model and a Monte Carlo-based modeling approach, and evaluated the reconstructed images using both the National Electrical Manufacturers Association NU 4-2008 standards and the Geant4 Application for Tomographic Emission simulation toolkit (GATE). An average full width at half maximum (FWHM) at different locations of 1.77 mm and 1.79 mm are obtained using the proposed system model and standard LOR system model, which does not include penetration effects, respectively. The standard deviation of the uniform region in the NEMA image quality phantom is 2.14% for the proposed method and 14.3% for the LOR system model, indicating that the proposed model out-performs the standard LOR-based model.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.11 no.1
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• pp.64-72
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• 2001

This paper is on a design of the high-speed cipher IC using IDEA algorithm. The chip is consists of six functional blocks. The principal blocks are encryption and decryption key generator, input data circuit, encryption processor, output data circuit, operation mode controller. In subkey generator, the design goal is rather decrease of its area than increase of its computation speed. On the other hand, the design of encryption processor is focused on rather increase of its computation speed than decrease of its area. Therefore, the pipeline architecture for repeated processing and the modular multiplier for improving computation speed are adopted. Specially, there are used the carry select adder and modified Booth algorithm to increase its computation speed at modular multiplier. To input the data by 8-bit, 16-bit, 32-bit according to the operation mode, it is designed so that buffer shifts by 8-bit, 16-bit, 32-bit. As a result of simulation by 0.25 $\mu\textrm{m}$ process, this IC has achieved the throughput of 1Gbps in addition to its small area, and used 12,000gates in implementing the algorithm.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.15 no.5
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• pp.3-11
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• 2005

This paper presents a performance analysis model based on an M/M/1 queue and Poisson distribution of input data traffic. The simulation on a pipelined AES system with processing rate of 10 rounds per clock shows $4.0\%$ higher performance than a non-pipelined version consuming 10 clocks per transaction. Physical implementation of pipelined AES with FPGA takes 3.5 times bigger gate counts than the non-pipelined version whereas the pipelined version yields only $3.5\%$ performance enhancement. The proposed analysis model can be used to optimize cost-performance of AES hardware designs.

• The Journal of the Korea institute of electronic communication sciences
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• v.17 no.3
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• pp.529-536
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• 2022

In the past two years, Severe Acute Respiratory Syndrome Coronavirus-2(SARS-CoV-2) has been hitting more and more to people. This paper proposes a novel U-Net Convolutional Neural Network to classify and segment COVID-19 lung CT images, which contains Sub Coding Block (SCB), Atrous Spatial Pyramid Pooling(ASPP) and Attention Gate(AG). Three different models such as FCN, U-Net and U-Net-SCB are designed to compare the proposed model and the best optimizer and atrous rate are chosen for the proposed model. The simulation results show that the proposed U-Net-MMFE has the best Dice segmentation coefficient of 94.79% for the COVID-19 CT scan digital image dataset compared with other segmentation models when atrous rate is 12 and the optimizer is Adam.

• Journal of IKEEE
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• v.26 no.2
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• pp.313-318
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• 2022

The feedback voltage detection structure is proposed to alleviate overshoot and undershoot caused by the removal of the existing external output capacitor. Conventional LDO regulators suffer from overshoot and undershoot caused by imbalances in the power supply voltage. Therefore, the proposed LDO is designed to have a more improved transient response to form a new control path while maintaining only the feedback path of the conventional LDO regulator. A new control path detects overshoot and undershoot events in the output stage. Accordingly, the operation speed of the pass element is improved by charging and discharging the current of the gate node of the pass element. LDO regulators with feedback voltage sensing architecture operate over an input voltage range of 3.3V to 4.5V and have a load current of up to 200mA at an output voltage of 3V. According to the simulation result, when the load current is 200mA, it is 73mV under the undershoot condition and 61mV under the overshoot condition.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.5
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• pp.682-687
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• 2022

In this paper, the research results on monolithic three-dimensional integrated-circuit (M3DICs) stacked with tunneling field effect transistors (TFETs) are introduced. Unlike metal-oxide-semiconductor field-effect transistors (MOSFETs), TFETs are designed differently from the layout of symmetrical MOSFETs because the source and drain of TFET are asymmetrical. Various monolithic 3D inverter (M3D-INV) structures and layouts are possible due to the asymmetric structure, and among them, a simple inverter structure with the minimum metal layer is proposed. Using the proposed M3D-INV, this M3D logic gates such as NAND and NOR gates by sequentially stacking TFETs are proposed, respectively. The simulation results of voltage transfer characteristics of the proposed M3D logic gates are investigated using mixed-mode simulator of technology computer aided design (TCAD), and the operation of each logic circuit is verified. The cell area for each M3D logic gate is reduced by about 50% compared to one for the two-dimensional planar logic gates.

• Proceedings of the Korea Water Resources Association Conference
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• 2021.06a
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• pp.329-329
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• 2021

우리나라의 농촌유역은 일반적으로 상류의 농업용저수지와 하류의 배수장을 통해 홍수조절이 이루어지며, 각 농업수리구조물의 운영이 유역의 홍수 및 침수 발생에 큰 영향을 끼친다. 농촌유역의 홍수 대응 능력을 향상시키기 위해서는 농업수리구조물의 통합적 운영이 필요하나 현실에서 이를 시험 운영하기 위해서는 시간적·경제적으로 한계가 있다. 따라서 농촌유역 내 농업수리구조물을 연계한 통합 해석 시스템을 활용하여 다양한 구조물 운영 시나리오에 따른 홍수 위험을 예측하고 효율적인 대응 방안을 마련할 필요가 있다. 본 연구에서는 농업수리구조물을 연계한 홍수·침수 모의 시스템을 구축하기 위하여, 농촌유역에서 홍수·침수 모의를 위한 요소별 모듈을 구성하고, 각 모듈의 연계 기술을 개발하였다. 홍수·침수 해석 모듈은 농업용저수지 상류 유역에서부터 하류 하천 및 농경지까지 통합적으로 분석할 수 있도록 강우 분석 모듈, 강우-유출 모듈, 저수지 운영 모듈, 하천 수위 모듈, 농경지 배수 모듈의 5가지로 구성하였으며, 데이터베이스 모듈을 통해 기초자료를 저장하고 모듈 간의 입출력 과정을 처리하였다. 강우 분석, 강우-유출, 농경지 배수 모듈은 python 코드를 기반으로 자체적으로 구축하였으며, 기존의 모형 (FARD, HEC-HMS, GATE2018)들과 비교한 결과 거의 동일한 모의 결과를 나타냈다. 저수지 운영 모듈과 하천 수위 모듈은 각각 미 공병단의 HEC-5, HEC-RAS 모형을 CLI (Command Line Interface) 방식으로 외부 구동하도록 구성하였다. 전체 모듈 간의 연계에는 python 라이브러리인 Dask를 적용하여 대량의 데이터에 대한 병렬 처리 구조를 갖춤으로써 다양한 기상자료와 운영 시나리오에 따른 반복 작업을 효율적으로 수행하도록 구성하였다. 본 연구에서 개발한 홍수·침수 모의 요소별 모듈과 연계 기술을 기반으로, 농업수리구조물의 연계 운영을 통합적으로 모의함으로써 홍수 대비를 위한 효율적인 구조물 운영안을 도출할 수 있을 것으로 기대된다.

• Journal of IKEEE
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• v.27 no.4
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• pp.601-609
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• 2023

In this paper, we propose an artificial intelligence-based high-speed fault diagnosis method using an FPGA in the event of a ground fault in a DC system. When applying artificial intelligence algorithms to fault diagnosis, a substantial amount of computation and real-time data processing are required. By employing an FPGA with AI-based high-speed fault diagnosis, the DC breaker can operate more rapidly, thereby reducing the breaking capacity of the DC breaker. therefore, in this paper, an intelligent high-speed diagnosis algorithm was implemented by collecting fault data through fault simulation of a DC system using Matlab/Simulink. Subsequently, the proposed intelligent high-speed fault diagnosis algorithm was applied to the FPGA, and performance verification was conducted.