• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.3
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• pp.176-186
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• 1996

As the density of VLSI increases, the conventional logic testing is not sufficient to completely detect the new faults generated in design and fabrication processing. Recently, IDDQ testing becomes very attractive since it can overcome the limitations of logic testing. In this paper, G-ATPG (gyeongsang automatic test pattern genrator) is designed which is able to be adapted to IDDQ testing for combinational CMOS VLSI. In G-ATPG, stuck-at, transistor stuck-on, GOS (gate oxide short)or bridging faults which can occur within priitive gate or XOR is modelled to primitive fault patterns and the concept of a fault-sensitizing gate is used to simulate only gates that need to sensitize the faulty gate because IDDQ test does not require the process of fault propagation. Primitive fault patterns are graded to reduce CPU time for the gates in a circuit whenever a test pattern is generated. the simulation results in bench mark circuits show that CPU time and fault coverage are enhanced more than the conventional ATPG using IDDQ test.

• Proceedings of the KIPE Conference
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• 2012.07a
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• pp.230-231
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• 2012

This paper describes a gate driver that operates numerous semiconductor switch in the solide-state pulsed power modulator. the proposed gate driver is designed to receive both the isolated drive-power and the on/off pulse signals through the transformer. Moreover, the IGBT-switch can be quickly turned off by adding protection circuit. Therefore it protects the IGBT-switch from the arc condition that frequently occurs in high-voltage pulse application. To comprehend operating characteristic of each IGBT-switch in pulse output condition, the device consisting of a high efficiency soft-switching capacitor charger and two series stacking IGBT-switch is developed. Finally, the relability of the proposed gate driver and the device for its test are proved through PSpice simulation and experiments.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.26 no.3
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• pp.190-193
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• 2013

Power MOSFET and Power IGBT is develop in power savings, high efficiency, small size, high reliability, fast switching, low noise. Power MOSFET can be used high-speed switching transistors devices. Power MOSFET is devices the voltage-driven approach switching devices are design to handle on large power, power supplies, converters. In this paper, design the 80V MOSFET Planar Gate type, and design the Trench Gate type for realization of low on-resistance. For both structures, by comparing and analyzing the results of the simulation and characterization.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.10a
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• pp.616-618
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• 2016

Four types of structure of tunnel field-effect transistors (TFETs) have been investigated by TCAD simulation. Pocket and L-shaped TFETs are better performance than single-gate and double-gate TFETs in terms of on-current and subthreshold swing. New guideline of TFETs is presented for the structure design.

• The Transactions of the Korean Institute of Power Electronics
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• v.27 no.1
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• pp.9-17
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• 2022

The series-connected semiconductor devices structure is one way to achieve a high voltage rating. However, a problem with voltage imbalance exists in which different voltages are applied to the series-connected switches. This paper proposed a new voltage balancing technique that controls the turn-off delay time of the switch by adding one bipolar junction transistor to the gate turn-off path. The validity of the proposed method is proved through simulation and experiment. The proposed active gate driver not only enables voltage balancing across a variety of current ranges but also has a greater voltage balancing performance compared with conventional RC snubber methods.

• Journal of the Korean Society of Radiology
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• v.14 no.5
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• pp.529-535
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• 2020

Geant4 is compatible with the Windows operating system in C++ language use, enabling interface functions that link DICOM or software. It was simulated to address the basic structure of the simulation using Geant4/Gate code and to specifically verify the density composition and lung cancer process in the human phantom. It was visualized using the Gate Graphic System, i.e. openGL, Ray Tracer: Ray Tracing by Geant4 Tracing, and using Geant4/Gate code, lung cancer is modeled in the human phantom area in 3D, 4D to verify the simulation progress. Therefore, as a large number of new functions are added to the Gate Code, it is easy to implement accurate human structure and moving organs.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.05a
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• pp.789-790
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• 2013

$Er_2O_3/SiO_2$ double-layer gate dielectric shows low gate leakage current and high capacitance. In this paper, we apply $Er_2O_3/SiO_2$ double-layer gate dielectric as a charge trap layer for the first time. $Er_2O_3/SiO_2$ double-layer thickness is optimized by EDISON Nanophysics simulation tools. Using the simulation results, we fabricated Schottky-barrier silicide source/drain transistor, which has10 um/10um gate length and width, respectively. The nonvolatile device demonstrated very promising characterstics with P/E voltage of 11 V/-11 V, P/E speed of 50 ms/500 ms, data retention of ten years, and endurance of $10^4$ P/E cycles.

• Journal of Navigation and Port Research
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• v.26 no.2
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• pp.177-182
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• 2002

In inner harbour of Incheon port, there are two lock gates (50KT, 10KT) which have two gates per lock gate in inner/outer sides except a gate in inner harbour side of 10KT. Due to the lack of the fore-mentioned gate, the use of 10KT lock gate is suspended in energy 3 years for regular maintenance. Now an additional gate is under construction in order to improve the efficiency of the 10KT lock gate. This paper will be aimed to evaluate the operational utilization levels of lock gates in present and future. The operational utilization levels of lock gates in 1998 are evaluated 0.2119 in 10KT lock gate, 0.2061 in 50KT lock gate which were considered the 46.5 closed days every 3 years for 10KT regular maintenance. The levels are estimated to 0.2246(10KT), 0.2539(50KT0 in 2006 and 0.2241(10KT), 0.2560(50KT) in 2011. The levels of 50KT lock gate in 2011 are evaluated to be more rapidly increased up to 24.5% from the levels in 1998.

• Journal of the Korean Ceramic Society
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• v.46 no.3
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• pp.229-233
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• 2009

This study has focused on manufacturing technique of powder injection molding of watch case made from zirconia powder. A series of computer simulation process was applied to prediction of the flow pattern in the inside of the mould to clarifying the change of sintering shrinkage depended on flow direction. The material properties of melted feedstock inclusive of the PVT graph and thermal viscosity flowage properties were measured for obtaining the input data in computer simulation. Also, molding experiment was conducted and the results of experiment showed that good agreement with simulation results for flow pattern and weld line location. On the other hand, gravity and inertia effect have an influence on velocity of melt front because of high density of ceramic powder particles in powder injection molding against the polymer injection molding process. In the experiment, the position of melt front was compared with upper gate and lower gate position. The gravity and inertia effect could be confirmed in the experimental results.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• 1998.10a
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• pp.107-115
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• 1998

For the purpose of building the simulation model on cargo handling capacity of container terminal, we composed a model of container logistics system which has a 4 subsystems ; cargo handling, transportation, storage system and Gate complex system. Several date used in simulation gained through spot research and basic statistic analysis using raw data from January to Jane in 1998. The results of this study are as follows ; First, average available ratio of each subsystem was G/C 50%, Y/T 57.5%, storage system 56%, Gate complex 50%, and there was no subsystem occurring specific bottleneck. Second, comparing the results of simulation to the results of basic statistics, we can verify suitability of this simulation model. Third, Comparing the results of this study to the results of existed study, we were able to confirm a change of BCTOC container logistics system under IMF situation.