• 반도체디스플레이기술학회지
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• 제12권3호
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• pp.23-27
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• 2013

This paper is for enhancing the breakdown voltage of MHEMTs with an InP-etchstop layer. Gate-recess structures has been simulated and analyzed for the breakdown of the devices with the InP-etchstop layer. The fully removed recess structure in the drain side of MHEMT shows that the breakdown voltage enhances from 2V to almost 4V and that the saturation current at gate voltage of 0V is reduced from 90mA to 60mA at drain voltage of 2V. This is because the electron-captured negatively fixed charges at the drain-side interface between the InAlAs barrier layer and the $Si_3N_4$ passivation layer deplete the InGaAs channel layer more and thus decreases the electron current passing the channel layer. In the paper, the fully-recessed asymmetric gate-recess structure at the drain side shows the on-breakdown voltage enhancement from 2V to 4V in the MHEMTs.

• Korea-Australia Rheology Journal
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• 제12권1호
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• pp.83-92
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• 2000

In resin transfer molding (RTM) process, preplaced fiber mat is set up in a mold and thermoset resin is injected into the mold. An important interest in RTM process is to minimize cycle time without sacrificing part quality or increasing cost. In this study, the numerical simulation and optimization process in filling stage were conducted in order to determine the optimum gate locations. Control volume finite element method (CVFEM) was used in this numerical analysis with the coordinate transformation method to analyze the complex 3-dimensional structure. Experiments were performed to monitor the flow front to validate simulation results. The results of numerical simulation predicted well the experimental results with every single, simultaneous and sequential injection procedure. We performed the optimization analysis for the sequential injection procedure to minimize fill time. The complex geometry of an automobile bumper core was chosen. Genetic algorithm was used in order to determine the optimum gate locations with regard to 3-step sequential injection case. These results could provide the information of the optimum gate locations in each injection step and could predict fill time and flow front.

• 센서학회지
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• 제27권6호
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• pp.362-367
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• 2018

A complementary metal oxide semiconductor (CMOS) binary image sensor is proposed for low-power and low-noise operation. The proposed binary image sensor has the advantages of reduced power consumption and fixed pattern noise (FPN). A gate/body-tied (GBT) p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET)-type photodetector is used as the proposed CMOS binary image sensor. The GBT PMOSFET-type photodetector has a floating gate that amplifies the photocurrent generated by incident light. Therefore, the sensitivity of the GBT PMOSFET-type photodetector is higher than that of other photodetectors. The proposed CMOS binary image sensor consists of a pixel array with $394(H){\times}250(V)$ pixels, scanners, bias circuits, and column parallel readout circuits for binary image processing. The proposed CMOS binary image sensor was analyzed by simulation. Using the dynamic comparator, a power consumption reduction of approximately 99.7% was achieved, and this performance was verified by the simulation by comparing the results with those of a two-stage comparator. Also, it was confirmed using simulation that the FPN of the proposed CMOS binary image sensor was successfully reduced by use of the double sampling process.

• Journal of Electrical Engineering and Technology
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• 제9권6호
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• pp.2070-2078
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• 2014

In this work, the frequency response of gate-all-around (GAA) Ge/GaAs heterojunction tunneling field-effect transistor (TFET) with hetero-gate-dielectric (HGD) and pnpn channel doping profile has been analysed by technology computer-aided design (TCAD) device-circuit mixed-mode simulations, with comparison studies among ppn, pnpn, and HGD pnpn TFET devices. By recursive tracing of voltage transfer curves (VTCs) of a common-source (CS) amplifier based on the HGD pnpn TFET, the operation point (Q-point) was obtained at $V_{DS}=1V$, where the maximum available output swing was acquired without waveform distortion. The slope of VTC of the amplifier was 9.21 V/V (19.4 dB), which mainly resulted from the ponderable direct-current (DC) characteristics of HGD pnpn TFET. Along with the DC performances, frequency response with a small-signal voltage of 10 mV has been closely investigated in terms of voltage gain ($A_v$), unit-gain frequency ($f_{unity}$), and cut-off frequency ($f_T$). The Ge/GaAs HGD pnpn TFET demonstrated $A_v=19.4dB$, $f_{unity}=10THz$, $f_T=0.487$ THz and $f_{max}=18THz$.

• 한국정보통신학회논문지
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• 제21권4호
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• pp.789-794
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• 2017

본 논문에서는 무접합 원통형 MOSFET의 해석학적 전위분포를 이용하여 문턱전압이하 전류모델을 제시하고 이를 이용하여 문턱전압이동을 해석하였다. 무접합 원통형 MOSFET는 채널을 게이트 단자가 감싸고 있기 때문에 캐리어 흐름을 제어하는 게이트 단자의 능력이 매우 우수하다. 본 연구에서는 쌍곡선 전위분포모델을 이용하여 포아송방정식을 풀고 이 때 얻어진 중심 전위분포를 이용하여 문턱전압이하 전류 모델을 제시하였다. 제시된 전류모델을 이용하여 $0.1{\mu}A$의 전류가 흐를 때 게이트 전압을 문턱전압으로 정의하고 2차원 시뮬레이션 값과 비교하였다. 비교결과 잘 일치하였으므로 이 전류모델을 이용하여 채널크기 및 도핑농도에 따라 문턱전압이동을 고찰하였다. 결과적으로 채널 반지름이 증가할수록 문턱전압이동은 매우 크게 나타났으며 산화막 두께가 증가할 경우도 문턱전압이동은 증가하였다. 채널 도핑농도에 따라 문턱전압을 관찰한 결과, 소스/드레인과 채널 간 도핑농도의 차이가 클수록 문턱전압은 크게 증가하는 것을 관찰하였다.

• 대한조선학회논문집
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• 제45권6호
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• pp.611-619
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• 2008

In most shipyards Floating Dock-gate System is adapted for dry docks. For the safe launching of ships in dry docks, smooth operation of dock-gate must be guaranteed. So it is very important to grasp its behavior in waves for securing the high productivity and the safety of workers. Its seakeeping ability was estimated numerically at the floating conditions and the free roll decay and the seakeeping model tests of dock-gate was carried out with bilge-keels of 3 different widths which have a scale of 1 to 20. More than 20% decrease of roll motion was observed in irregular beam seas by applying a bilge-keel system to the dock-gate that is long and narrow.

• 한국방재학회:학술대회논문집
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• 한국방재학회 2008년도 정기총회 및 학술발표대회
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• pp.791-794
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• 2008

하천에 위치하는 취수장의 수질관리에 있어서 오염물질의 이송-확산은 주요 관심사다. 오염물 이송에 관한 연구를 위해서는 하천의 사행에 따른 영향과 지류의 유입에 따른 혼합에 대해서 분석이 수행되어져야 한다. 본 연구의 목적은 낙동강 하류에 위치한 물금취수장 부근에서의 오염물의 혼합거동을 모의하고자 하였다. 물금취수장은 부산광역시의 음용수로써 이용되고 있으며, 물금취수장 인근에서의 흐름은 인근의 지천의 유입과 본류 유량, 그리고 하류단에 위치한 하구둑 수문개폐 여부의 영향을 받는다. 수문은 10개의 수문으로 구성되며, 평상시에는 조위에 따라서 보조수문을 개방하고 유량이 증가할 때 주수문을 함께 개방한다. 취수장 맞은편인 본류의 우안에는 지류인 대포천이 위치하는데 지류에서 발생한 오염물질은 취수장 인근에 흐름형태에 따라 취수구로 유입되기도 한다. 본 연구에서는 2차원 수치해석 결과를 바탕으로 오염사고에 대비한 적절한 취수장 운영방안을 제시하고자 하였다.

• 전기전자학회논문지
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• 제25권4호
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• pp.774-777
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• 2021

본 논문은 Charge Trap Flash using Ferroelectric(CTF-F) 구조를 가진 3D NAND Flash Memory gate controllability에 대해 분석했다. Ferroelectric 물질인 HfO₂는 polarization 이외에도 high-k 라는 특징을 가진다. 이러한 특징으로 인해 CTF-F 구조에서 gate controllability가 증가하고 Bit Line(BL)에서 on/off 전류특성이 향상된다. Simulation 결과 CTF-F 구조에서 String Select Line(SSL)과 Ground Select Line(GSL)의 채널길이는 100 nm로 기존 CTF 구조에 비해 33% 감소했지만 거의 동일한 off current 특성을 확인했다. 또한 program operation에서 channel에 inversion layer가 더 강하게 형성되어 BL을 통한 전류가 약 2배 증가한 것을 확인했다.

• 대한전자공학회논문지SD
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• 제48권10호
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• pp.54-61
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• 2011

본 논문에서는 intrinsic-body cylindrical/surrounding gate SOI MOSFET의 I-V 특성 도출을 위한 간단한 해석적 모델을 제시하였다. Intrinsic 실리콘 채널 영역에서의 Poisson 방정식과 gate oxide 내에서의 Laplace 방정식을 해석적으로 풀어 소스와 드레인 양단 끝에서의 표면 전위 분포를 bisection method를 이용하여 구하였다. 구해진 표면 전위를 바탕으로 closed-form의 I-V 특성 식을 도출하였다. 도출된 I-V 특성 표현 식을 모의 실험한 결과, 소자의 parameter와 가해진 bias 전압에 대한 비교적 정확한 의존성을 확인할 수 있었다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제11권4호
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• pp.278-286
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• 2011

In this paper, we present a compact model of gate-voltage-dependent quantum effects in short-channel surrounding-gate (SG) metal-oxide-semiconductor field-effect transistors (MOSFETs). We based the model on a two-dimensional (2-D) analytical solution of Poisson's equation using cylindrical coordinates. We used the model to investigate the electrostatic potential and current sensitivities of various gate lengths ($L_g$) and radii (R). Schr$\ddot{o}$dinger's equation was solved analytically for a one-dimensional (1-D) quantum well to include quantum effects in the model. The model takes into account quantum effects in the inversion region of the SG MOSFET using a triangular well. We show that the new model is in excellent agreement with the device simulation results in all regions of operation.