• Journal of the Korea Institute of Information and Communication Engineering
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• v.24 no.2
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• pp.268-275
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• 2020

A lightweight hardware design of self-timed ring based true random number generator (TRNG) suitable for information security applications is described. To reduce hardware complexity of TRNG, an entropy extractor with feedback structure was proposed, which minimizes the number of ring stages. The number of ring stages of the FSTR-TRNG was determined to be a multiple of eleven, taking into account operating clock frequency and entropy extraction circuit, and the ratio of tokens to bubbles was determined to operate in evenly-spaced mode. The hardware operation of FSTR-TRNG was verified by FPGA implementation. A set of statistical randomness tests defined by NIST 800-22 were performed by extracting 20 million bits of binary sequences generated by FSTR-TRNG, and all of the fifteen test items were found to meet the criteria. The FSTR-TRNG occupied 46 slices of Spartan-6 FPGA device, and it was implemented with about 2,500 gate equivalents (GEs) when synthesized in 180 nm CMOS standard cell library.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.23 no.12
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• pp.1609-1617
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• 2019

Described in this paper is a design of hardware accelerator for implementing public-key cryptographic protocols (PKCPs) based on Elliptic Curve Cryptography (ECC) and RSA. It supports five elliptic curves (ECs) over GF(p) and three key lengths of RSA that are defined by NIST standard. It was designed to support four point operations over ECs and six modular arithmetic operations, making it suitable for hardware implementation of ECC- and RSA-based PKCPs. In order to achieve small-area implementation, a finite field arithmetic circuit was designed with 32-bit data-path, and it adopted word-based Montgomery multiplication algorithm, the Jacobian coordinate system for EC point operations, and the Fermat's little theorem for modular multiplicative inverse. The hardware operation was verified with FPGA device by implementing EC-DH key exchange protocol and RSA operations. It occupied 20,800 gate equivalents and 28 kbits of RAM at 50 MHz clock frequency with 180-nm CMOS cell library, and 1,503 slices and 2 BRAMs in Virtex-5 FPGA device.

• Journal of IKEEE
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• v.26 no.2
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• pp.313-318
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• 2022

The feedback voltage detection structure is proposed to alleviate overshoot and undershoot caused by the removal of the existing external output capacitor. Conventional LDO regulators suffer from overshoot and undershoot caused by imbalances in the power supply voltage. Therefore, the proposed LDO is designed to have a more improved transient response to form a new control path while maintaining only the feedback path of the conventional LDO regulator. A new control path detects overshoot and undershoot events in the output stage. Accordingly, the operation speed of the pass element is improved by charging and discharging the current of the gate node of the pass element. LDO regulators with feedback voltage sensing architecture operate over an input voltage range of 3.3V to 4.5V and have a load current of up to 200mA at an output voltage of 3V. According to the simulation result, when the load current is 200mA, it is 73mV under the undershoot condition and 61mV under the overshoot condition.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.12
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• pp.1914-1919
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• 2021

With the development of advanced industries, research on image processing hardware is essential, and timing verification at the gate level is required for actual chip operation. For FPGA-based verification, DDR3 memory interface was previously applied. But recently, as the FPGA specification has improved, DDR4 memory is used. In this case, when a previously used memory interface is applied, the timing mismatch of signals may occur and thus cannot be used. This is due to the difference in performance between CPU and memory. In this paper, the problem is solved through state optimization of the existing interface system FSM. In this process, data read speed is doubled through AXI Data Width modification. For actual case analysis, ZC706 using DDR3 memory and ZCU106 using DDR4 memory among Xilinx's SoC boards are used.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.5
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• pp.682-687
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• 2022

In this paper, the research results on monolithic three-dimensional integrated-circuit (M3DICs) stacked with tunneling field effect transistors (TFETs) are introduced. Unlike metal-oxide-semiconductor field-effect transistors (MOSFETs), TFETs are designed differently from the layout of symmetrical MOSFETs because the source and drain of TFET are asymmetrical. Various monolithic 3D inverter (M3D-INV) structures and layouts are possible due to the asymmetric structure, and among them, a simple inverter structure with the minimum metal layer is proposed. Using the proposed M3D-INV, this M3D logic gates such as NAND and NOR gates by sequentially stacking TFETs are proposed, respectively. The simulation results of voltage transfer characteristics of the proposed M3D logic gates are investigated using mixed-mode simulator of technology computer aided design (TCAD), and the operation of each logic circuit is verified. The cell area for each M3D logic gate is reduced by about 50% compared to one for the two-dimensional planar logic gates.

• The Journal of the Convergence on Culture Technology
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• v.7 no.2
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• pp.351-357
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• 2021

At the time when interest in the use of big data is rising in the face of the technological paradigm shift of the 4th industrial revolution, interest in the use of patented big data is increasing, especially as the proportion of intangible assets of companies increases. In addition to quantitative information, patent data contains various information such as unstructured text such as title, abstract, claim, citation and citation relations, drawings, and technology classification. It is judged that the use of treatment is important. Therefore, in this study, in order to systematically operate the innovative patent strategy framework and to secure a competitive advantage by strengthening the fundamental technological competitiveness of the company, we propose a method of using patent big data centering on the case of Company A, and verify its validity. I would like to suggest some implications. Through this, it is intended to raise awareness of the use of patent big data, and to suggest ways to use patent big data in connection with the company's company-wide strategy, business strategy, and functional strategy.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.7
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• pp.955-961
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• 2021

In modern warfare, the importance of electronic warfare, which carries out a mission that using radio wave to find out enemy information or to protect ally information, has increased. Radar jamming technique is one of the most representative techniques of EA(Electronic Attack), it disturbs and deceives enemy radar system in order to secure ally location information. Velocity deception jamming technique, which is one of the radar jamming techniques, generally operate against pulse-doppler radar which use doppler effect in order to track target's velocity and location. Velocity Deception Jamming Technique can be implemented using DRFM(Digital Radio Frequency Memory) that performs Frequency Modulation. In this paper, I describe implementation method of VGPO/VGPI(Velocity Gate Pull-Off/Pull-In) velocity deception jamming technique using phase-sampled DRFM, and verify the operation of VGPO/VGPI velocity deception jamming technique with board test under signal injection condition.

• International conference on construction engineering and project management
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• 2009.05a
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• pp.1278-1282
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• 2009

In apartment type of housing, if resident's vehicle is registered in central control office and RFID TAG is issued, identification can be recognized from the time of entrance into parking lot and intelligent parking guide system can be activated based on the residents' profile. Parking Guide System leads a vehicle to the available parking space which is closest to the entrance gate of the vehicle's owner. And when residents forget where they parked their cars, they can query to the Parking Guide and Management System and get responses about the location. For the correct operation of this system, it is necessary to find out where the residents' cars have parked in real time and which lot is available for parking of other cars. RFID is very fancy solution for this system. RFID reader gathers the ID information in RFID TAGs in parked cars and updates the DB up to date. But, when non-residents' cars are parked inside apartment, RFID reader cannot identify them nor know the exact empty/occupied status of parking spaces because they don't react to RFID reader's query. So for the exact detection of empty/occupied status, we suggest the combined use of ultrasonic sensors and RFID. We designed a tree topology with intermediate data aggregators. The depth of tree is normally more than 3 from root (central office) to leaves (individual parking lots). The depth of 2 in tree topology brings about the bottleneck in communication and maintenance. We also designed the information fields used in RFID networks and Sensor Networks.

• Progress in Superconductivity
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• v.4 no.1
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• pp.1-9
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• 2002

Transferring single flux quanta across a Josephson junction at an exactly determined rate has made highly precise voltage measurements possible. Making use of self-shunted Nb-based SINIS junctions, programmable fast-switching DC voltage standards with output voltages of up to 10 V were produced. This development is now extended from fundamental DC measurements to the precise determination of AC voltages with arbitrary waveforms. Integrated RSFQ circuits will help to replace expensive semiconductor devices for frequency control and signal coding. Easy-to-handle AC and inexpensive quantum voltmeters of fundamental accuracy would be of interest to industry. In analogy to the development in the flux regime, metallic nanocircuits comprising small-area tunnel junctions and providing the coherent transport of single electrons might play an important role in quantum current metrology. By precise counting of single charges these circuits allow prototypes of quantum standards for electric current and capacitance to be realised. Replacing single electron devices by single Cooper pair circuits, the charge transfer rates and thus the quantum currents could be significantly increased. Recently, the principles of the gate-controlled transfer of individual Cooper pairs in superconducting A1 devices in different electromagnetic environments were demonstrated. The characteristics of these quantum coherent circuits can be improved by replacing the small aluminum tunnel Junctions by niobium junctions. Due to the higher value of the superconducting energy gap ($\Delta_{Nb}$ ＝ $7\Delta_{Al}$), the characteristic energy and the frequency scales for Nb devices are substantially extended as compared to A1 devices. Although the fabrication of small Nb junctions presents a real challenge, the Nb-based metrological devices will be faster and more accurate in operation. Moreover, the Nb-based Cooper pair electrometer could be coupled to an Nb single Cooper pair qubit which can be beneficial for both, the stability of the qubit and its readout with a large signal-to-noise ratio..

• Journal of the Korea Society of Computer and Information
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• v.14 no.12
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• pp.201-208
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• 2009

As the ubiquitous environment is created, the latest ports introduce U-Port services in managing ports generally and embody container's location identification system, port terminal management system, and advanced information exchange system etc. In particular, the location identification system for freight cars and containers provide in real time the information on the location and condition for them, and enables them to cope with an efficient vehicle operation management and its related problems immediately. However, such a system is insufficient in effectively handling with the troubles in a large-scale port including freight car's disorderly driving, parking, stop, theft, damage, accident, trespassing and controlling. In order to solve these problems, this study structures the vehicle positioning system and the image verification system unsing high resolution image compression and AVE/H.264 store and transmission technology, able to mark and identify the vehicle location on the digital map while a freight car has stayed in a port since the entry of an automatic gate, or able to identify the place of accident through image remotely.