• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.16 no.1
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• pp.13-19
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• 2002

The plasma display panel with the electrode structure of new discharge AND gate was proposed and the driving system for experiment was developed. And discharge AND gate operation was verified. Discharge AND gate operated by the operation speed of 8${\mu}\textrm{s}$ and the operation margin of 20V. It was known to be able to control the discharge of the adjoining scan electrode accurately. Because this method uses the DC discharge, the control of the discharge can be facilitated compared with conventional discharge AND gate. Moreover, because the input discharge and the output discharge of AND gate are separate, the display discharge can be prevented from passing AND gate. Therefore it is possible to app1y to the large screen plasma display. And the decrease of contrast ratio does not occur because the scanning discharge does not influence the picture quality.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.21 no.11
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• pp.226-232
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• 2020

The Stage-Gate is a market-oriented model that aims to launch new products on the market. Therefore, it can be appropriately introduced and applied to the operation and management of NSSCP, which is undergoing demonstration projects for Daegu and Siheung. In addition, smart cities have the characteristics of convergence and complex among various innovative technologies. When the Stage-Gate is introduced, the performance can be managed centering on the outcomes for each research institution. Therefore, the NSSCP is applying the Stage-Gate for the first time among national R&D projects to improve the quality of the research results and to demonstrate and commercialize them successfully. This paper reviews the operation results of the 1st and 2nd years when the State-Gate was introduced and analyzes the opinions of an R&D management agency, research institutes, and gate reviewers to present the supplementary and improvements for applying to the evaluation process for the next year. When operating the Stage-Gate by optimizing the situation for each project and being wary of inefficiencies caused by the rigid operation, it is expected that flexible evaluation for each outcome will be possible according to the convergence characteristics of smart cities.

• Journal of Sensor Science and Technology
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• v.30 no.1
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• pp.61-65
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• 2021

In this study, we propose a 2500 frame per second (fps) high-speed binary complementary metal oxide semiconductor (CMOS) image sensor using a gate/body-tied (GBT) p-channel metal oxide semiconductor field effect transistor-type high-speed photodetector. The GBT photodetector generates a photocurrent that is several hundred times larger than that of a conventional N+/P-substrate photodetector. By implementing an additional binary operation for the GBT photodetector with such high-sensitivity characteristics, a high-speed operation of approximately 2500 fps was confirmed through the output image. The circuit for binary operation was designed with a comparator and 1-bit memory. Therefore, the proposed binary CMOS image sensor does not require an additional analog-to-digital converter (ADC). The proposed 2500 fps high-speed operation binary CMOS image sensor was fabricated and measured using standard CMOS process.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.11a
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• pp.463-466
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• 2000

According to the development of the semiconductor micro device technology, IC chip trends the high integrated, low power tendency. Nowadays, it can be showed the tendency of single chip in system level. But in the system level, IC operates by multi power supply voltages. So, semiconductor process is necessary for these multi power operation. Therefore, in this paper, dual gate high voltage device that operate by multi power supply of 5V and 20V fabricated in the 0.5${\mu}{\textrm}{m}$ CMOS process technology and its electrical characteristics were analyzed. The result showed that the characteristics of the 5V device almost met with the SPICE simulation, the SPICE parameters are the same as the single 5V device process. And the characteristics of 20V device showed that gate length 3um device was available without degradation. Its current was 520uA/um, 350uA/um for NMOS, PMOS and the breakdown voltages were 25V, 28V.

• The Transactions of the Korean Institute of Power Electronics
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• v.19 no.4
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• pp.376-382
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• 2014

This paper proposes the pulse width modulation (PWM) control strategy for low-speed operation in the three-level neutral-point-clamped (NPC) inverters based on the bootstrap gate drive circuit. As a purpose of the cost reduction, several papers have paid attention to the bootstrap circuit applied to the three-level NPC inverter. However, the bootstrap gate driver IC cannot generate the gate signal to the IGBT for low-speed operation, because the bootstrap capacitor voltage decreases under the threshold level. For low-speed operation, the dipolar and partial-dipolar modulations can be the effective solution. However, these modulations have drawbacks in terms of the switching loss and THD. Therefore, this paper proposes the PWM control strategy to operate the inverter at low-speed and to minimize the switching loss and harmonics. The experimental results are presented to verify the validity on the proposed method.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.3
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• pp.195-203
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• 2005

Recently, a novel multi-bit nonvolatile memory based on double gate (DG) MOSFET is proposed to overcome the short channel effects and to increase the memory density. We need more complex voltage schemes for DG MOSFET devices. In view of peripheral circuits driving memory cells, one should consider various voltage sources used for several operations. It is one of the key issues to minimize the number of voltage sources. This criterion needs more caution in considering a DG nonvolatile memory cell that inevitably requires more number of events for voltage sources. Therefore figuring out the permissible range of operating bias should be preceded for reliable operation. We found that reliable operation largely depends on the depletion conditions of the silicon channel according to charge amount stored in the floating gates and the negative control gate voltages applied for read operation. We used Silvaco Atlas, a 2D numerical simulation tool as the device simulator.

• Ecology and Resilient Infrastructure
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• v.7 no.4
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• pp.300-307
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• 2020

This study was conducted to evaluate the impact of weir gate operation in aquatic fish habitats through a physical habitat simulation of Geum River, Korea. The target species was Zacco platypus, which is a dominant species in the study area. The River2D model was used to compute the flow, and the habitat suitability index model was used to estimate the quality and quantity of the habitat using a habitat suitability curve. An unopened case and a partially opened case were investigated to assess the impact of weir gate operation on the aquatic fish habitat. The simulation results showed that the aquatic habitats of the target species in the partially opened case improved significantly, compared to the case without a gate opening. Furthermore, the weighted usable area increased by a factor of approximately 13, owing to weir gate operation in the study area.

• Journal of The Korean Society of Agricultural Engineers
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• v.47 no.6
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• pp.15-24
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• 2005

The normalization on the characteristics of water level change at the upstream gauging station was attempted according to the operation of drainage sluice gate of the Geumgang estuary dam. The characteristics were normalized by the analysis of water level change and by the linear-regression of the water level data measured at the inner station of Geumgang estuary dam and upstream gauging station. The results of normalization may be referred to the management of Geumgang estuary lake, the operation of pumping and drainage stations in the shore of the lake. The mean response time of water level change on Ibpo, Ganggyeong and Gyuam water level station were 39,81 and 160 minutes, when sluice gate was opened respectively. The mean velocity of surface wave, the mean displacement of water level change, the mean time of water level change and the mean rate of water level change varied largely depending on the location of gauging station and the characteristics of stream section of the water level gauging station.

• Proceedings of the Korea Water Resources Association Conference
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• 2008.05a
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• pp.26-32
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• 2008

Middle Route Project, the largest water conveyance system in China delivers the water of Changjiang River to North China. In order to create canal operation simulation system, mathematical models are established based on the analysis of hydraulics about steady flow, unsteady flow, and check gate. By simulating the canal operation behavior, we improved the check gate control algorithm and predicted the change process of water surface and flow profile which is very valuable to actual canal operation.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.2
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• pp.104-110
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• 2008

In this paper we proposed a new source-drain structure for N-type MOSFET which can suppress the output resistance reduction of a device in saturation region due to soft break down leakage at high drain voltage when the gate is biased around relatively low voltage. When a device is generally used as a switch at high gate bias the current level is very important for the operation. but in electronic circuit like an amplifier we should mainly consider the output resistance for the stable voltage gain and the operation at low gate bias. Hence with T-SUPREM simulator we designed devices that operate at low gate bias and high gate bias respectively without a extra photo mask layer and ion-implantation steps. As a result the soft break down leakage due to impact ionization is reduced remarkably and the output resistance increases about 3 times in the device that operates at the low gate bias. Also it is expected that electronic circuit designers can easily design a circuit using the offered N-type MOSFET device with the better output resistance.