• Current Photovoltaic Research
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• v.3 no.3
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• pp.80-84
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• 2015

We suggest new emitter formation method using solid-phase epitaxy (SPE); solid-phase epitaxy emitter (SEE). This method expect simplification and cost reduction of process compared with furnace process (POCl3 or BBr3). The solid-phase epitaxy emitter (SEE) deposited a-Si:H layer by radio-frequency plasma-enhanced chemical vapor deposition (RF-PECVD) on substrate (c-Si), then thin layer growth solid-phase epitaxy (SPE) using rapid thermal process (RTP). This is possible in various emitter profile formation through dopant gas ($PH_3$) control at deposited a-Si:H layer. We fabricated solar cell to apply solid-phase epitaxy emitter (SEE). Its performance have an effect on crystallinity of phase transition layer (a-Si to c-Si). We confirmed crystallinity of this with a-Si:H layer thickness and annealing temperature by using raman spectroscopy, spectroscopic ellipsometry and transmission electron microscope. The crystallinity is excellent as the thickness of a-Si layer is thin (~50 nm) and annealing temperature is high (<$900^{\circ}C$). We fabricated a 16.7% solid-phase epitaxy emitter (SEE) cell. We anticipate its performance improvement applying thin tunnel oxide (<2nm).

• Journal of Sensor Science and Technology
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• v.15 no.6
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• pp.379-385
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• 2006

Single crystal of p-$CdIn_{2}Te_{4}$ was grown in a three-stage vertical electric furnace by using Bridgman method. The quality of the grown crystal has been investigated by x-ray diffraction and photoluminescence measurements. From the photoluminescence spectra of the as-grown $CdIn_{2}Te_{4}$ crystal and the various heat-treated crystals, the ($D^{o}$, X) emission was found to be the dominant intensity in the photoluminescence spectrum of the $CdIn_{2}Te_{4}$:Cd, while the ($A^{o}$, X) emission completely disappeared in the $CdIn_{2}Te_{4}$:Cd. However, the ($A^{o}$, X) emission in the photoluminescence spectrum of the $CdIn_{2}Te_{4}$:Te was the dominant intensity like in the as-grown $CdIn_{2}Te_{4}$ crystal. These results indicated that the ($D^{o}$, X) is associated with $V_{Te}$ which acted as donor and that the ($A^{o}$, X) emission is related to $V_{Cd}$ which acted as acceptor, respectively. The p-$CdIn_{2}Te_{4}$ crystal was obviously found to be converted into n-type after annealing in Cd atmosphere. The origin of ($D^{o},{\;}A^{o}$) emission and its to phonon replicas is related to the interaction between donors such as $V_{Te}$ or $Cd_{int}$, and acceptors such as $V_{Cd}$ or $Te_{int}$. Also, the In in the $CdIn_{2}Te_{4}$ was confirmed not to form the native defects because it existed in a stable bonding form.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.396-396
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• 2013

The resistive random access memory (ReRAM) has several advantages to apply next generation non-volatile memory device, because of fast switching time, long retentions, and large memory windows. The high mobility of monolayered graphene showed several possibilities for scale down and electrical property enhancement of memory device. In this study, the monolayered graphene grown by chemical vapor deposition was transferred to $SiO_2$ (100 nm)/Si substrate and glass by using PMMA coating method. For formation of metal-oxide nanoparticles, we used a chemical reaction between metal films and polyamic acid layer. The 50-nm thick BPDA-PDA polyamic acid layer was coated on the graphene layer. Through soft baking at $125^{\circ}C$ or 30 min, solvent in polyimide layer was removed. Then, 5-nm-thick indium layer was deposited by using thermal evaporator at room temperature. And then, the second polyimide layer was coated on the indium thin film. After remove solvent and open bottom graphene layer, the samples were annealed at $400^{\circ}C$ or 1 hr by using furnace in $N_2$ ambient. The average diameter and density of nanoparticle were depending on annealing temperature and times. During annealing process, the metal and oxygen ions combined to create $In_2O_3$ nanoparticle in the polyimide layer. The electrical properties of $In_2O_3$ nanoparticle ReRAM such as current-voltage curve, operation speed and retention discussed for applictions of transparent and flexible hybrid ReRAM device.

• Proceedings of the KIEE Conference
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• 1998.07g
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• pp.2536-2538
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• 1998

This paper investigates the residual stress of tetraethoxysilane (TEOS) and 7wt% phosphosilicate glass (PSG), which are commonly used as a sacrificial layer or etch mask in the fabrication of microelectromechanical systems (MEMS). In order to measure residual stress, $2{\mu}m$ thick TEOS and PSG stress measurement structures are fabricated. Polysilicon is used as the sacrificial layer. First the residual stress of an as-deposited 7wt% PSG flim and TEOS film are measured to be-0.3115% and -0.435%, respectively, which are quite large. These films are annealed from $500^{\circ}C$ to $800^{\circ}C$. Annealing has the effects of reducing residual stress. In the case of the 7wt% PSG film, the residual stress becomes +0.00715% after annealing at $625^{\circ}C$ for 150 minutes. In the case of TEOS film, the residual stress reduces to -0.2134% after same condition. Incidentally, this condition is the same condition for depositing a $2{\mu}m$ thick polysilicon at $625^{\circ}C$ at our low pressure chemical vapor deposition (LPCVD) furnace.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.8-9
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• 2006

Hafnium oxide ($HfO_2$) thin films were deposited on p-type (100) silicon wafers by atomic layer deposition (ALD) using TEMAHf and $O_3$. Prior to the deposition of $HfO_2$ films, a thin Hf ($10\;{\AA}$) metal layer was deposited. Deposition temperature of $HfO_2$ thin film was $350^{\circ}C$ and its thickness was $150\;{\AA}$. Samples were then annealed using furnace heating to temperature ranges from 500 to $900^{\circ}C$. The MOS capacitor of round-type was fabricated on Si substrates. Thermally evaporated $3000\;{\AA}$-thick AI was used as top electrode. In this work, We study the interface characterization of $HfO_2$/Hf/Si MOS capacitor depending on annealing temperature. Through AES(Auger Electron Spectroscopy), capacitance-voltage (C-V) and current-voltage (I-V) analysis, the role of Hf layer for the better $HfO_2$/Si interface property was investigated. We found that Hf meta1 layer in our structure effective1y suppressed the generation of interfacial $SiO_2$ layer between $HfO_2$ film and silicon substrate.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.171-171
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• 2010

GaN 기반 Light emitting diodes(LEDs)의 p-type doping layer는 일반적으로 hole을 발생시키는 acceptor로 Mg이 사용하되고 있다. 보통 Mg이 도핑된 p-type GaN은 >$1\;{\Omega}{\cdot}cm$의 저항이 존재하는데 그 이유는 Mg의 열적 이온화를 위한 activation 에너지가 높아서 상온에서 valence band의 hole concentration는 전체 억셉터 농도의 1%가 되지 않기 ��문이다. 본 논문에서는 높은 hole 농도를 얻기 위해서 metalorganic chemical-vapor deposition (MOCVD)를 장비를 사용하여 사파이어 기판의 misorientation-angle에 따른 p-type a-plane(11-20) GaN 특성을 분석하였다. misorientation-angle은 c축 방향으로 $+0.15^{\circ}$, $-0.15^{\circ}$, $-0.2^{\circ}$, $-0.4^{\circ}$ off된 r-plane(1-102) 사파이어 기판 을 사용하였다. p-type 도핑물질로 bis-magnesium (Cp2Mg) 소스를 사용하였고 성장 과정중 발생하는 hydrogen passivation으로 인한 Mg-H complexes현상을 해결하기위해 conventional furnace annealing (CFA)와 rapid thermal annealing (RTA)를 이용하여 열처리 공정을 진행하였다. 열처리 공정은 Air와 N2 분위기에서 $650^{\circ}C$에서 $900^{\circ}C$ 사이의 다양한 온도에서 수행하였고 Hall 측정을 위해 Ni을 전극 물질로 사용하였다. 상온에서 Accent HL5500IU Hall system을 사용하여 hole concentration, mobility, specific resistance을 측정하였다. 열처리 공정 후 Hall측정 결과 $+0.15^{\circ}$, $-0.15^{\circ}$, $-0.2^{\circ}$, $-0.4^{\circ}$ off된 각 샘플들은 온도, 시간, 분위기에 따라 hole concentration ($7.4{\times}10^{16}cm^{-3}{\sim}6{\times}10^{17}cm^{-3}$), mobility(${\mu}h=\;1.72\;cm^2/V-s\;{\sim}15.2\;cm^2/V-s$), specific resistance(4.971 ohm-cm ~8.924 ohm-cm) 가 변화됨을 확인 할 수 있었다. 또한 광학적 특성을 분석하기 위해 Photoluminescence (PL)을 측정하였다.

• Journal of Convergence for Information Technology
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• v.9 no.3
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• pp.75-81
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• 2019

In this work, we investigated a low temperature polycrystalline silicon (LTPS) thin film transistors fabrication process on polymer layers. Dehydrogenation and activation processes were performed by a furnace annealing at a temperature of $430^{\circ}C$ for 2 hr. The crystallization of amorphous silicon films was formed by excimer laser annealing (ELA) method. The p-type device performance, fabricated by polycrystalline silicon (poly-Si) films, shows a very good performance with field effect mobility of $77cm^2/V{\cdot}s$ and on/off ratio current ratio > $10^7$. We believe that the poly-Si formed by a LTPS process may be well suited for fabrication of poly-Si TFTs for bendable panel displays such as AMOLED that require circuit integration.

• Journal of the Korean Vacuum Society
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• v.21 no.5
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• pp.273-278
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• 2012

Over the last decade, the hafnium-based gate dielectric materials have been studied for many application fields. Because these materials had excellent behaviors for suppressing the quantum-mechanical tunneling through the thinner dielectric layer with higher dielectric constant (high-K) than $SiO_2$ gate oxides. Although high-K materials compensated the deterioration of electrical properties for decreasing the thickness of dielectric layer in MOSFET structure, their nano-mechanical properties of $HfO_2$ thin film features were hardly known. Thus, we examined nano-mechanical properties of the Hafnium oxide ($HfO_2$) thin film in order to optimize the gate dielectric layer. The $HfO_2$ thin films were deposited by rf magnetron sputter using hafnium (99.99%) target according to various oxygen gas flows. After deposition, the $HfO_2$ thin films were annealed after annealing at $400^{\circ}C$, $600^{\circ}C$ and $800^{\circ}C$ for 20 min in nitrogen ambient. From the results, the current density of $HfO_2$ thin film for 8 sccm oxygen gas flow became better performance with increasing annealing temperature. The nano-indenter and Weibull distribution were measured by a quantitative calculation of the thin film stress. The $HfO_2$ thin film after annealing at $400^{\circ}C$ had tensile stress. However, the $HfO_2$ thin film with increasing the annealing temperature up to $800^{\circ}C$ had changed compressive stress. This could be due to the nanocrystal of the $HfO_2$ thin film. In particular, the $HfO_2$ thin film after annealing at $400^{\circ}C$ had lower tensile stress, such as 5.35 GPa for the oxygen gas flow of 4 sccm and 5.54 GPa for the oxygen gas flow of 8 sccm. While the $HfO_2$ thin film after annealing at $800^{\circ}C$ had increased the stress value, such as 9.09 GPa for the oxygen gas flow of 4 sccm and 8.17 GPa for the oxygen gas flow of 8 sccm. From these results, the temperature dependence of stress state of $HfO_2$ thin films were understood.

• Korean Journal of Materials Research
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• v.4 no.2
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• pp.143-151
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• 1994

On PT/Ti/Si substrates, PZT thln fllms are deposited at $300^{\circ}C$ by rf magnetron sputtering uslng a $(PbZr_{52}, Ti_{48})O_{3}$ composltc cerarnlc target. To abtaln, the stable phase, perovskltc structure, furnace annealmg techmque had been cmplo:~d In PbO amb~ent for the $550^{\circ}C$-$750^{\circ}C$ temperature ranges. On Pt(250$\AA$)/Ti(500$\AA$)/Si, Pt(1000)$\AA$/Ti(500$\AA$)/Si substrates, effects of Ti layer and Pt thickness are studled. Though thickness of the Pt layer 1s 1000$\AA$). oxygen diffusion is not prevented and accelerated by Ti layer actlng for oxygen sink sites durmg furnace annealing. The upper TI layer 1s transformed Into TIOX by oxyen dlffuslon and lower Ti layer Into silicide with in-diffused Pt. The formation of TiOx layer seems to affect the orlentatton of the PZT layer. Furnace annealed f~lm shows ferroelectr~c and electrical properties wth a remanent polarlzation of 3.3$\mu A /\textrm{cm}^2$, , coerclve fleld of 0.15MV/cm, a=571 (10kHz), leakage current 32.65$\mu A /\textrm{cm}^2$, , breakdown voltage of 0.4OMV/cm.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.28A no.12
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• pp.31-38
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• 1991

The current-voltage characteristics at annealed Be-Cu alloy(1.8-2 wt% Be, 0.2 wt% Co+Ni) interfaces have been studied by means of the cyclic voltammetric method. The specimens were annealed in nitrogen gas($N_{2}$) furnace at 36$0^{\circ}C$ for 1.5 hours. After annealing, the vickers hardness(HV) was increased from 210 to 385. The used solutions were distilled water(H$_{2}$O), 10$^{-3}M\;CsNO_{2},10^{-2}M\;KCl,10^{-2}M\;KOH,10^{-4}M\;H_{2}SO_{4}$ aqueous electrolytes, and ethylalcohol ($C_{2}H_{5}OH$), etc. The cyclic voltammograms showed significant current-voltage characteristics between the annealed and unannealed specimens at the same conditions. The age hardening and the related surface potential barrer and dissolution effects have been observed during the whole experimental process. The dissolution process of annealed Be-Cu alloys was effectively retarded by the age hardening phenomenon. The age hardening effect also raised the surface potential barrier of Be-Cu alloys. The interfacial phenomena of Be-Cu alloys seem to be one of good models for understanding the activation process.