• BMB Reports
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• v.30 no.3
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• pp.194-199
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• 1997

Previous studies have shown that the HD3 human enterocytic differentiated colon carcinoma cell lines having low $PKC{\beta}$ activity did not respond to diacylglycerol and basic FGF by growth and by activation of pp57 MAP kinase, but undifferentiated cell lines exhibiting high $PKC{\beta}$ activity did. To confirm a role of $PKC{\beta}$ in colonocyte mitogenesis, derivatives of HD3 cell line that stably overexpress a full-length of cDNA encoding the ${\beta}_1$ isoform of human PKC were generated. The abundance and activity of $PKC{\beta}$ in two of the these cell lines, PKC3 and PKC8 were much higher than those in the C1 control cell line that carries the vector lacking the $PKC{\beta}_1\;cDNA$ insert. Following exposure to diacylglycerol or basic FGF, proliferation of PKC3 and PKC8 cells increased about 50%; but this effect was not seen with the control C1 cells. Also, in contrast to the control cells, the $PKC{\beta}_1-overproducing$ cells displayed activation of pp57 MAP kinase when treated with diacylglycerol and basic FGF as undifferentiated cell lines did. These results provide direct evidence that $PKC{\beta}_1$ which plays a key role in mitogenic responses of colon carcinoma cells to diacylglycerol and basic FGF is down-regulated in enterocytic differentiation of colon cells.

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.2
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• pp.65-70
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• 2015

In this paper, we describe the world's first real-time ray-tracing chip architecture. Ray-tracing technology generates high-quality 3D graphics images better than current rasterization technology by providing four essential light effects: shadow, reflection, refraction and transmission. The real-time ray-tracing chip named RayChip includes a real-time ray-tracing graphics processing unit and an accelerating tree-building unit. An ARM Ltd. central processing unit (CPU) and other peripherals are also included to support all processes of 3D graphics applications. Using the accelerating tree-building unit named RayTree to minimize the CPU load, the chip uses a low-end CPU and decreases both silicon area and power consumption. The evaluation results with RayChip show appropriate performance to support real-time ray tracing in high-definition (HD) resolution, while the rendered images are scaled to full HD resolution. The chip also integrates the Linux operating system and the familiar OpenGL for Embedded Systems application programming interface for easy application development.

• Journal of the Institute of Convergence Signal Processing
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• v.16 no.1
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• pp.1-8
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• 2015

In many image processing tasks, connected component labeling (CCL) is performed to extract regions of interest. CCL was usually done in a sequential fashion when image resolution was relatively low and there are small number of input channels. As image resolution gets higher up to HD or Full HD and as the number of input channels increases, sequential CCL is too time-consuming to be used in real time applications. To cope with this situation, parallel CCL framework was introduced where multiple cores are utilized simultaneously. Several parallel CCL methods have been proposed in the literature. Among them are NSZ label equivalence (NSZ-LE) method[1], modified 8 directional label selection (M8DLS) method[2], and HYBRID1 method[3]. Soh [3] showed that HYBRID1 outperforms NSZ-LE and M8DLS, and argued that HYBRID1 is by far the best. In this paper we propose an improved hybrid parallel CCL algorithm termed as HYBRID2 that hybridizes M8DLS with label backtracking (LB) and show that it runs around 20% faster than HYBRID1 for various kinds of images.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.9 no.10
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• pp.3887-3907
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• 2015

This paper introduces a full duplex single secondary user multiple-input multiple-output (FD-SSU-MIMO) cognitive radio network, where secondary user (SU) opportunistically accesses the authorized spectrum unoccupied by primary user (PU) and transmits data based on FD-MIMO mode. Then we study the network achievable average sum-rate maximization problem under sum transmit power budget constraint at SU communication nodes. In order to solve the trade-off problem between SU's sensing time and data transmission time based on opportunistic spectrum access (OSA) and the power allocation problem based on FD-MIMO transmit mode, we propose a simple trisection algorithm to obtain the optimal sensing time and apply an alternating optimization (AO) algorithm to tackle the FD-MIMO based network achievable sum-rate maximization problem. Simulation results show that our proposed sensing time optimization and AO-based optimal power allocation strategies obtain a higher achievable average sum-rate than sequential convex approximations for matrix-variable programming (SCAMP)-based power allocation for the FD transmission mode, as well as equal power allocation for the half duplex (HD) transmission mode.

• Journal of Convergence for Information Technology
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• v.11 no.12
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• pp.90-96
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• 2021

In this paper, we designed manufactured and design an integrated interface control unit that has compatibility with brightness control unit, color control unit, and existing control unit. As the implementation method the standard of DVI/HDMI transmission method is applied to the data transmission method, and the Sil 1169 IC is used as the applied IC. Brightness control is programmed to have eight levels of brightness control using the AT89C2051. Also, EPM240T100C5 IC was used for image and dimming data processing. As a result, it is compatible with the control unit using the DVI/HDMI transmission method manufactured by each company and can reproduce clear high quality full HD video according to the surrounding brightness through the full color LED display system.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.12C
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• pp.1020-1028
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• 2010

Relay has attracted great attention due to its inherent capability to extend the service coverage and combat shadowing in next generation mobile communication systems. So far, most relay technologies have been developed under the half-duplex (HD) constraint that prevents relays from transmitting and receiving at the same time. Although half-duplex relay (HDR) is easy to implement, it requires partitioning of resource for transmission and reception, reducing the whole system capacity. In this paper, we propose a multinser precoding and power control scheme with sum rate matching for a full-duplex (FD) multiple-input multiple-output (MIMO) relay. Full-duplex relay (FDR) can overcome the drawback of HDR by transmitting and receiving on the same frequency at the same time, while it is crucial to reduce the effect of self-interference that is caused by its own transmitter to its own receiver. The proposed precoding scheme cancels the self-interference of the FDR as well as to support multiuser MIMO. Moreover, we suggest a power allocation scheme for FD MIMO relay with the constraint that the sum rate of the relay's received data streams is equal to that of the relay's transmit data streams.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.11 no.11
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• pp.5338-5359
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• 2017

In-band full-duplex (IBFD) wireless communication supports symmetric dual transmission between two nodes and asymmetric dual transmission among three nodes, which allows improved throughput for distributed IBFD wireless networks. However, inter-node interference (INI) can affect desired packet reception in the downlink of three-node topology. The current Half-duplex (HD) medium access control (MAC) mechanism RTS/CTS is unable to establish an asymmetric dual link and consequently to suppress INI. In this paper, we propose a medium access control mechanism for use in distributed IBFD wireless networks, FD-DMAC (Full-Duplex Distributed MAC). In this approach, communication nodes only require single channel access to establish symmetric or asymmetric dual link, and we fully consider the two transmission modes of asymmetric dual link. Through FD-DMAC medium access, the neighbors of communication nodes can clearly know network transmission status, which will provide other opportunities of asymmetric IBFD dual communication and solve hidden node problem. Additionally, we leverage FD-DMAC to transmit received power information. This approach can assist communication nodes to adjust transmit powers and suppress INI. Finally, we give a theoretical analysis of network performance using a discrete-time Markov model. The numerical results show that FD-DMAC achieves a significant improvement over RTS/CTS in terms of throughput and delay.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.5
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• pp.430-442
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• 2013

This paper presents a fast multi-reference frame integer motion estimator for H.264/AVC. The proposed system uses the previously proposed fast multi-reference frame algorithm. The previously proposed algorithm executes a full search area motion estimation in reference frames 0 and 1. After that, the search areas of motion estimation in reference frames 2, 3 and 4 are minimized by a linear relationship between the motion vector and the distances from the current frame to the reference frames. For hardware implementation, the modified algorithm optimizes the search area, reduces the overlapping search area and modifies a division equation. Because the search area is reduced, the amount of computation is reduced by 58.7%. In experimental results, the modified algorithm shows an increase of bit-rate in 0.36% when compared with the five reference frame standard. The pipeline structure and the memory controller are also adopted for real-time video encoding. The proposed system is implemented using 0.13 um CMOS technology, and the gate count is 1089K with 6.50 KB of internal SRAM. It can encode a Full HD video ($1920{\times}1080P@30Hz$) in real-time at a 135 MHz clock speed with 5 reference frames.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.23 no.2
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• pp.45-52
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• 2009

This study is related to the realization of high speed address driving method for Full-HD PDP. The new self-priming addressing(SPA) driving scheme was proposed to improve an address discharge time lag, which utilizes the priming effect maintaining the priming discharge during an address period. In this study, the basic characteristics of the priming ramp discharge were investigated and optimize the reset pulse and priming pulse. It is noted that the address discharge time lag is significantly improved from 1.2[${\mu}s$] to 0.8[${\mu}s$] when the slope of the priming ramp pulse is below 0.1[$V/{\mu}s$].

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.1
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• pp.28-34
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• 2015

Several parallelization methods that can be applied to High Efficiency Video Coding (HEVC) decoders are evaluated. The market requirements of high-resolution videos, such as Full HD and UHD, have been increasing. To satisfy the market requirements, several parallelization methods for HEVC decoders have been studied. Understanding these parallelization methods and objective comparisons of these methods are crucial to the real-time decoding of high-resolution videos. This paper introduces the parallelization methods that can be used in HEVC decoders and evaluates the parallelization methods comparatively. The experimental results show that the average speed-up factors of tile-level parallelism, wavefront parallel processing (WPP), frame-level parallelism, and 2D-wavefront parallelism are observed up to 4.59, 4.00, 2.20, and 3.16, respectively.