IEIE Transactions on Smart Processing and Computing

대한전자공학회 (The Institute of Electronics and Information Engineers)
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Performance Analysis of HEVC Parallelization Methods for High-Resolution Videos

  • Ryu, Hochan (Department of Computer Engineering, Kwangwoon University) ;
  • Ahn, Yong-Jo (Department of Computer Engineering, Kwangwoon University) ;
  • Mok, Jung-Soo (Department of Computer Engineering, Kwangwoon University) ;
  • Sim, Donggyu (Department of Computer Engineering, Kwangwoon University)
  • 투고 : 2014.04.05
  • 심사 : 2014.11.19
  • 발행 : 2015.02.28
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초록

Several parallelization methods that can be applied to High Efficiency Video Coding (HEVC) decoders are evaluated. The market requirements of high-resolution videos, such as Full HD and UHD, have been increasing. To satisfy the market requirements, several parallelization methods for HEVC decoders have been studied. Understanding these parallelization methods and objective comparisons of these methods are crucial to the real-time decoding of high-resolution videos. This paper introduces the parallelization methods that can be used in HEVC decoders and evaluates the parallelization methods comparatively. The experimental results show that the average speed-up factors of tile-level parallelism, wavefront parallel processing (WPP), frame-level parallelism, and 2D-wavefront parallelism are observed up to 4.59, 4.00, 2.20, and 3.16, respectively.

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참고문헌

  1. High Efficiency Video Coding, Rec. ITU-T H.265 and ISO/IEC 23008-2, Jan 2013.
  2. J. Lainema, F. Bossen, W. Han, J. Min, and K. Ugur, "Intra Coding of the HEVC Standard," IEEE Trans. Circuits Syst. Video Technol., vol. 22, no. 12, pp.1792-1801, Dec. 2012. https://doi.org/10.1109/TCSVT.2012.2221525
  3. G.J. Sullivan, J.-R. Ohm, W.-J. Han, and T. Wiegand, "Overview of the High Efficiency Video Coding (HEVC) standard," IEEE Trans. Circuits Syst. Video Technol., vol. 22, no. 12, pp.1648-1667, Dec. 2012.
  4. C. Fu, E. Alshina, A. Alshin, Y. Huang, C. Chen, and C. Tsai, C. Hsu, S. Lei, J. Park, and W. Han, "Sample adaptive offset in the HEVC standard," IEEE trans. on Circuits and Systems for Video Technol., vol. 22, no. 12, pp. 1755-1764, Dec. 2012. https://doi.org/10.1109/TCSVT.2012.2221529
  5. J.-R. Ohm, G. J. Sullivan, H. Schwarz, T.K. Tan, and T. Wiegan, "Comparison of the coding efficiency of video coding standards-Including High Efficiency Video Coding (HEVC)," IEEE Trans. Circuits Syst. Video technol., vol. 22, no. 12, pp. 1668-1683, Dec. 2012.
  6. Y. Ahn, T. Hwang, D. Sim, and W. Han, "Implementation of fast HEVC encoder based on SIMD and data-level parallelism," EURASIP Journal on Image and Video Processing, March. 2014.
  7. E. Ryu, J. Nam, S. Lee, H. Jo, and D. Sim, "Sample adaptive offset parallelism in HEVC," International Conference on Green and Human Information Technology (ICGHIT 2013), Hanoi, Vietnam, Feb. 27- Mar. 1, 2013.
  8. H. Jo and D. Sim, "Hybrid Parallelization for HEVC Decoder," Image and Signal Processing (CISP)., vol. 1, pp. 170-175, Dec. 2012.
  9. E. Baaklini, H. Sbeity, and S. Niar, "H.264 Macroblock Line Level Parallel Video Decoding on Embedded Multicore Processors," Digital System Design (DSD), pp. 902-906, Sep. 2012.
  10. B. Bross, W.-J, Han, G.J. Sullivan, J.-R. Ohm, and T. Wiegand, "High Efficiency Video Coding (HEVC) Text Specification Draft 10 (for FDIS & Last Call,"document JCTVC-L1003_v34, Geneva, CH, Jan. 2013.
  11. K. Misra, A. Segall, M. Horowiz, S. Xu, A. Fuldseth and M. Zhou, "An Overvidw of Tiles in HEVC," IEEE Selected Topics in Signal Processing, vol. 7, pp. 969-977, Nov. 2013. https://doi.org/10.1109/JSTSP.2013.2271451
  12. C. Chi, M. Alvarez-Mesa, B. Juulink, G. Clare, F. Henry, S. Pateux, and T. Schierl, "Parallel Scalability and Efficiency of HEVC Parallelization Approaches," IEEE Trans. Circuits Syst. Video Technol., vol. 22, no. 12, pp. 1827-1838, Dec. 2012. https://doi.org/10.1109/TCSVT.2012.2223056
  13. A. Norkin, G. Bjøntegaard, A. Fuldseth, M. Narroschke, M. Ikeda, K. Andersson, M. Zhou, and G. Auwera, "HEVC deblocking filter," IEEE trans. on Circuits and Systems for Video Technol., vol. 22, no. 12, pp. 1746-1754, Dec. 2012. https://doi.org/10.1109/TCSVT.2012.2223053
  14. J. Boyce, et al., "Draft high efficiency video coding (HEVC) version 2, combined format range extensions (RExt), scalability (SHVC), and multiview (MV-HEVC) extensions," JCTVC-R1013, 18th JCT-VC meeting, Sapporo, JP, June 2014.
  15. ITU-T Q6/16 and ISO/IEC JTC1/SC29/WG11 document N14175, "Joint Call for Proposals for Coding of Screen Content," San Jose, USA, Jan. 2014.
  16. T. Wiegand, G. J. Sullivan, G.Bjontegaard, and A. Luthra, "Overview of the H.264/AVC Video Coding Standard," IEEE Transactions on Circuits and Systems for Video Technology, vol. 13, no. 7, pp. 560-576, Jul. 2003. https://doi.org/10.1109/TCSVT.2003.815165
  17. F. Bossen, B. Bross, K. Suhring, and D. Flynn, "HEVC complexity and implementation analysis," IEEE trans. on Circuits and Systems for Video Technology, vol. 22, no. 12, pp. 1685-1696, Dec. 2012. https://doi.org/10.1109/TCSVT.2012.2221255
  18. H. Jo and D. Sim, "Bitstream decoding processor for fast entropy decoding of variable length coding-based multiformat videos," Optical Engineering on Imaging Components, Systems, and Processing, vol. 53, no. 6, June 2014.
  19. HM-12.0, https://hevc.hhi.fraunhofer.de/svn/svn_HEVCSoftware/tags/HM-12.0
  20. L. Dagum and R. Menon, "OpenMP: an industry standard API for shared-memory programming," IEEE Computational Science & Engineering, vol. 5, no. 1, pp.46-55, Jan. 1998. https://doi.org/10.1109/99.660313

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  2. Load Balancing Based on Transform Unit Partition Information for High Efficiency Video Coding Deblocking Filter vol.39, pp.3, 2017, https://doi.org/10.4218/etrij.17.0116.0638
  3. Tile-level rate control for tile-parallelization HEVC encoders pp.1861-8219, 2017, https://doi.org/10.1007/s11554-017-0720-5
  4. Software pipelining with CGA and proposed intrinsics on a reconfigurable processor for HEVC decoders pp.1861-8219, 2017, https://doi.org/10.1007/s11554-017-0729-9
  5. Fast mode decision and early termination based on perceptual visual quality for HEVC encoders pp.1861-8219, 2019, https://doi.org/10.1007/s11554-017-0694-3