• 한국정보처리학회:학술대회논문집
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• 한국정보처리학회 2000년도 추계학술발표논문집 (상)
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• pp.465-468
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• 2000

본 논문에서는 인식코드를 전송할 수 있는 modulator 뿐만 아니라 Reader system으로부터 코드 전송제어 명령어를 수신할 수 있고 향후 EEPROM과 더불어 인식코드를 수정할 수 있는 RFID (Radio Frequency IDentification) Transponder 칩 설계에 관한 내용을 다룬다. RFID칩은 배터리를 사용하지 않고 명령어와 함께 형성되는 Field로부터 전원을 생성하고 동시에 코드를 제공하는 Full-Duplex 구조로 설계하였다. Transponder IC는 power-generation 회로, clock generation 회로, digital block, modulator, overvoltage protection 회로로 구성된다. 설계된 칩은 저전력 회로를 적용하여 원거리 transponder칩을 구현할 수 있도록 하였다. 설계된 회로는 $0.6{\mu}m$ 현대 CMOS 공정으로 레이아웃 하였으며 제작중에 있다.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2005년도 International Meeting on Information Displayvol.I
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• pp.727-731
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• 2005

Design and manufacturing process of a full color LED microdislay fabricated by standard CMOS technology and containing an array of aluminum / nanostructured porous silicon reverse biased light emitting Schottky diodes will be discussed. Being of a solid state construction, this microdisplays are cost-effective, thin and light in weight due to very simple device architecture. Its benefits include also super high resolution, wide viewing angles, fast response time and wide operating temperature range. The advantages of full integration of an LED-array and driving circuitry onto a Si-chip will be also discussed.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2008년도 학술대회 논문집 정보 및 제어부문
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• pp.217-218
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• 2008

Since the digital TV signal band is very wide ($54{\sim}806MHz$), the VCO used in the frequency synthesizer must also have a wide frequency tuning range. Multiple LC VCOs have been used to cover such wide frequency band. However, the chip area increases due to the increased number of integrated inductors. A general method for achieving both reduced VCO gain(Kvco) and wide frequency band is to use the switched-capacitor bank LC VCO. In this paper, a scheme is proposed to cover the full band using only one VCO. The RF VCO block designed using a 0.18um CMOS process consists of a wideband LC VCO with reduced variation of VCO gain and frequency steps. Buffers, divide-by-2 circuits and control logics the simulation results show that the designed circuit has a phase noise at 100kHz better than -106dBc/Hz throughout the signal band and consumes $9.5{\sim}13mA$ from a 1.8V supply.

• 대한전자공학회논문지SD
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• 제39권7호
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• pp.89-96
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• 2002

본 논문은 ELA알고리듬의 수평방향 및 수직방향과 대각선 방향을 판단하여 수평 윤곽선 및 수직 윤곽선 특성을 시각적인 면과 객관적인 면에서 개선한 ADI(adaptive de-interlacing)알고리듬을 제안하고, 제안한 알고리듬에 대한 수직을 전개, 이를 C, Matlab을 이용하여 검증하였다. 제안한 알고리듬의 구조를 $0.6{\mu}m$ 2-poly 3-metal CMOS 표준 라이브러리를 적용하고 Cadence툴을 이용하여 회로 및 논리 시뮬레이션을 수행하고 레이아웃을 작성하였다.

• 전자공학회논문지A
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• 제28A권1호
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• pp.40-45
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• 1991

It is well known that the conventional differential source-coupled pair uses gates as its input terminals. This input pair provids a high open-loop gain, a large CMRR, and a good PSRR. For these reasons, the input pair has been used widely as an input stages of the differential amplifiers, but a narrow linear input range of this structurelimits its application in the area of some analog circuit design. A novel CMOS source-coupled backgate pair is proposed in this paper. The bulk of MOSFET is exploited and input devices are biased to operate in ohmic region. With this topology, the backgate pair of the wide linear input range and variable transconductance can be obtained. This backgate input differential stage is realized with the size of W/L=50/25 MOSFETs. The results show the nonlinear error is less than $\gamma$1% over 10V full-scale range for the bias current of 200$\mu$A with 10V single power-supply.

• JSTS:Journal of Semiconductor Technology and Science
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• 제4권1호
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• pp.41-44
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• 2004

The trend of decreasing the minimal structure sizes in microelectronics is still being continued. Therefore in its roadmap the Semiconductor Industries Association predicts a printed minimum MOS-transistor channel length of 10 nm for the year 2018. Although the resolution of optical lithography still dramatically increases, there are known and proved solutions for structure sizes significantly below 50 nm up to now. In this work a new method for the fabrication of extremely small MOS-transistors with a channel length and width below 50 nm with low demands to the used lithography will be explained. It's a further development of our deposition and etchback technique which was used in earlier research to produce transistors with very small channel lengths down to 30 nm, with a scaling of the transistor's width. The used technique is proved in a first charge of MOS-transistors with a channel area of W=200 nm and L=80 nm. The full CMOS compatible technique is easily transferable to almost any other technology line and results in an excellent homogeneity and reproducibility of the generated structure size. The electrical characteristics of such small transistor will be analyzed and the ultimate limits of the technique will be discussed.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2007년도 심포지엄 논문집 정보 및 제어부문
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• pp.195-196
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• 2007

Since the digital TV signal band is very wide ($54{\sim}806MHz$), the VCO used in the frequency synthesizer must also have a wide frequency tuning range. Multiple LC VCOs have been used to cover such wide frequency band. However, the chip area increases due to the increased number of integrated inductors. In this paper, a scheme is proposed to cover the full band using only one VCO. The RF VCO block designed using a 0.18um CMOS process consists of a wideband LC VCO, five divide-by-2 circuits and several buffers. The simulation results show that the designed circuit has a phase noise at 10kHz better than -87dBc/Hz throughout the signal band and consumes 10mA from a 1.8V supply.

• 센서학회지
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• 제19권3호
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• pp.209-213
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• 2010

This paper describes the fabrication and characteristics of AlN piezoelectric MPG(micro power generator). The micro energy harvester was fabricated to convert ambient vibration energy to electrical power as a AlN piezoelectric cantilever with Si proof-mass. To be compatible with CMOS process, AlN thin film was grown at low temperature by RF magnetron sputtering and micro power generators were fabricated by MEMS technologies. X-ray diffraction pattern proved that the grown AlN film had highly(002) orientation with low value of FWHM(full width at the half maximum, $\theta=0.276^{\circ}$) in the rocking curve around(002) reflections. The implemented harvester showed the $198.5\;{\mu}m$ highest membrane displacement and generated 6.4 nW of electrical power to $80\;k{\Omega}$ resistive load with $22.6\;mV_{rms}$ voltage from 1.0 G acceleration at its resonant frequency of 389 Hz. From these results, the AlN piezoelectric MPG will be possible to suitable with the batch process and confirm the possibility for power supply in portable, mobile and wearable microsystems.

• 대한전자공학회논문지SD
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• 제44권3호
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• pp.26-34
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• 2007

본 논문에서는 신체 임피던스 측정법(Bioelectrical Impedance Analysis, 이하 BIA)을 기초로 한 체지방 측정 칩 설계에 대한 내용을 서술하였다. 제안된 회로는 인체에 전류 신호를 인가하는 회로, 인체를 통해 나온 전압 신호를 측정하는 회로, 회로의 동작을 제어하는 마이크로 콘트롤러(Micom), 그리고 분석프로그램이 내장된 메모리(SRAM, EEPROMs) 의 모든 기능을 하나의 칩에 집적하였다. 특히 정밀한 인체 임피던스 측정을 위하여 다주파수 동작이 가능한 대역통과필터(Band Pass Filter, BPF)를 설계하였다. 또한, 설계된 대역통과필터는 weak inversion 영역에서 동작하기 때문에 면적과 전력소모를 줄일 수 있었다. 그리고 측정부분 회로의 성능을 개선하기 위해서 차동차이증폭기(Differential difference amplifier, DDA)를 이용한 새로운 전파정류기(Full wave rectifier, FWR)를 설계하였다. 또한 이 회로는 마지막 단에 연결될 아날로그-디지털 변환기(ADC)의 설계에 대한 부담을 덜어주는 장점도 있다. 이 칩의 시제품은 CMOS 0.35um 공정을 이용하였고 전력소모는 모든 주파수에서 6mW 이며 전원전압은 3.3V이다. 전체 칩의 크기는 $5mm\times5mm$ 이다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권4호
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• pp.497-505
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• 2016

The two-dimensional (2D) Discrete Cosine Transform (DCT) is used widely in image and video processing systems. The perception of human visualization permits us to design approximate rather than exact DCT. In this paper, we propose a digital implementation of 16-point approximate 2D DCT architecture based on one-dimensional (1D) DCT and Modified Gate Diffusion Input (MGDI) technique. The 8-point 1D Approximate DCT architecture requires only 12 additions for realization in digital VLSI. Additions can be performed using the proposed 8 transistor (8T) MGDI Full Adder which reduces 2 transistors than the existing 10 transistor (10T) MGDI Full Adder. The Approximate MGDI 2D DCT using 8T MGDI Full adders is simulated in Tanner SPICE for $0.18{\mu}m$ CMOS process technology at 100MHZ.The simulation result shows that 13.9% of area and 15.08 % of power is reduced in the 8-point approximate 2D DCT, 10.63 % of area and 15.48% of power is reduced in case of 16-point approximate 2D DCT using 8 Transistor MGDI Full Adder than 10 Transistor MGDI Full Adder. The proposed architecture enhances results in terms of hardware complexity, regularity and modularity with a little compromise in accuracy.