• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.6
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• pp.7-12
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• 2010

A semi-empirical organic schottky diode model is proposed for circuit simulation. We have set up a full custom design environment for organic schottky diode circuit using Spectre AHDL, which is widely used commercial EDA tool. We measured frequency response from fabricated rectifier, and it was compared to circuit simulation results using the AHDL model. The frequency response of the fabricated rectifier circuit is not sufficient for 13.56MHz RFID, however, it is enough for 135kHz-band RFID.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.7
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• pp.89-96
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• 2002

In this paper, the ADI(Adaptive De-interlacing) algorithm is proposed, which improves visually and subjectively horizontal and vertical edges of the image processed by the ELA(Edge Line-based Average) method. This paper also proposes a VLSI architecture for the proposed algorithm and the architecture designed through the full custom CMOS layout process. The proposed algorithm is verified using C and Matlab and implemented using $0.6{\mu}m$ 2-poly 3-metal CMOS standard libraries. For the circuit and logic simulation, Cadence tool is used.

• ETRI Journal
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• v.31 no.4
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• pp.478-480
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• 2009

The design of a CMOS clamped-clamped beam resonator along with a full custom integrated differential amplifier, monolithically fabricated with a commercial 0.35 ${\mu}m$ CMOS technology, is presented. The implemented amplifier, which minimizes the negative effect of the parasitic capacitance, enhances the electrical MEMS characterization, obtaining a $48{\times}10^8$ resonant frequency-quality factor product ($Q{\times}f_{res}$) in air conditions, which is quite competitive in comparison with existing CMOS-MEMS resonators.

• International Journal of CAD/CAM
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• v.6 no.1
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• pp.173-181
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• 2006

In this paper, an integration framework of Geometric Constraint Solving Engine and AutoCAD is presented, and a dynamic geometric constraint system is introduced. According to inherent orientation features of geometric entities and various Object Snap results of AutoCAD, the' proposed system can automatically construct an under-constrained geometric constraint model during interactive drawing. And then the directed constraint graph in a geometric constraint model is realtime modified in order to produce an optimal constraint solving sequence. Due to the open object-oriented characteristics of AutoCAD, a set of user-defined entities including basic geometric elements and graphics constraint relations are defined through derivation. And the custom-made Object Reactor and Command Reactor are also constructed. Several powerful characteristics are achieved based on these user-defined entities and reactors, including synchronously processing geometric constraint information while saving and opening DWG files, visual constraint relations, and full adaptability to Undo/Redo operations. These characteristics of the proposed system can help the designers more easily manage geometric entities and constraint relations between them.

• Fashion & Textile Research Journal
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• v.19 no.4
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• pp.411-420
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• 2017

With the increasing popularization of low-priced luxury markets, maintaining the genuine values of luxury has become crucial for luxury fashion brands to attract customers who want exclusivity and rarity. The world-leading luxury fashion houses have employed a variety of experiential marketing strategies like special order product strategies and mobile SNS promotion strategies, yet little research exists on there the strategies actually positively impact brand luxury images and customer attitudes towards the brand. This study empirically analyzed the effects of customer experience of special order products on perceived brand luxury and brand relationship. Furthermore, the study also tested relationships among perceived brand luxury, brand relationship, and brand loyalty. A survey was conducted with Korean female consumers who had purchase experiences of special order products from the brands. We analyzed the data of MTO-experienced respondents due to the lack of respondents who had experienced custom-made product services. The result indicates the significant effect of experience of MTO on brand relationship; however, we found only a partial support for the effect of MTO on brand luxury. Likewise, we found a partial support for the effect of mobile SNS promotion strategies on perceived brand luxury versus full support for the effect on brand relationship.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.7
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• pp.1718-1731
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• 1998

Digital quadrature demodulator is needed for the coherent demodulation in the digital communication systems such as Binary Phase-Shift-Keying, Quadrature Phase-Shift-Keying, and Quadrature Anmplitude Modulation. Conventaionally, the DDFS (Direct Digital Frequency Synthsizer) is used for generating the carrier signal and seperate multi-pliers are used for mixing. And the DDFS is implemented using the ROM (Read Only Memory), which can be a bottle-neck neck when the fast-speed and small-area implementation is required. A new architecture is developed, which employs the circular rotation mode of the CORDIC algorithm for signal mixing as well as carrier generation. To optimize the hardware design parameters, the finiteword-length effects of the proposed implementation arachitecture are analyzed in comparison with a conventional ROM-based architecture. The hardware costs are also estimated, which showed that the proposed architecture occupies only a third of the area of the conventional ROM-based architecture for the same performance. A full-custom VLSI is developed using the proposed architecture.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.11A
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• pp.929-935
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• 2003

An analog/digital mixed mode ASIC for network synchronization of ATM switching system has been designed and fabricated. This ASIC generates a 234.7/46.94 ㎒ system clock and 77.76/19.44 ㎒ user clock using 46.94 ㎒ transmitted clocks from other systems. It also includes digital circuits for checking and selecting of the transmitted clocks. For effective ASIC design, full custom technique is used in 2 analog PLL circuits design, and standard cell based technique is used in digital circuit design. Resistors and capacitors for analog circuits are specially designed which can be fabricated in general CMOS technology, so the chip can be implemented in 0.8$\mu\textrm{m}$ digital CMOS technology with no expensive. Testing results show stable 234.7 ㎒ and 19.44 ㎒ clocks generation with each 4㎰ and 17㎰ of low ms jitter.

• The Journal of Information Technology
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• v.6 no.4
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• pp.11-23
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• 2003

We proposes that Design of the Digital Neuron Processor and Development of the Algorithm for the real time object recognition in the making Automatic system which uses the residue number system making the high speed operation possible without carry propagation, in this paper. Consisting of MAC(Multiplication and Accumulation) operator unit using Residue number system and sigmoid function operator unit using Mixed Residue Conversion is designed. The Designed circuits are descripted by C language and VHDL and synthesized by Compass tools. Finally, the designed processor is fabricated in 0.8${\mu}m$ CMOS process. Result of simulations shows that critical path delay time is about 19nsec and operation speed is 0.6nsec and the size can be reduced to 1/2 times co pared to the neural networks implemented by the real number operation unit. The proposed design the digital neuron processor can be implemented of the object recognition in the making Automatic system with desired real time processing.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.12
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• pp.54-60
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• 2007

This paper proposes a built-in-self-repair (BISR) structure using 2-dimensional spare memory to effectively self-repair faults of an embedded memory. In case of multiple faults in the same row (column) of an embedded memory, the previous method using 1-D spare column (row) memory needs the same number of spare memory columns (rows) as the number of faults to self-repair them. while the new method using 2-D spare memory needs only one spare row (column) to self-repair them. Also, the virtual divided memory is adopted to be able to self-repair using not a full spare column memory but the only partial spare column memory corresponding to the faults. A self-repair circuit with $64\times1-bit$ core memory and $2\times8$ 2-D spare memory is designed. And the circuit includes a built-in-self-test block using the 13N March algorithm. The circuit has been implemented using the $0.25{\mu}m$ MagnaChip CMOS process and has $1.1\times0.7mm^2$ chip area with 10,658 transistors.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1993.06a
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• pp.975-976
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• 1993

This talk presents the overview of the author's research and development activities on fuzzy inference hardware. We involved it with two distinct approaches. The first approach is to use application specific integrated circuits (ASIC) technology. The fuzzy inference method is directly implemented in silicon. The second approach, which is in its preliminary stage, is to use more conventional microprocessor architecture. Here, we use a quantitative technique used by designer of reduced instruction set computer (RISC) to modify an architecture of a microprocessor. In the ASIC approach, we implemented the most widely used fuzzy inference mechanism directly on silicon. The mechanism is beaded on a max-min compositional rule of inference, and Mandami's method of fuzzy implication. The two VLSI fuzzy inference chips are designed, fabricated, and fully tested. Both used a full-custom CMOS technology. The second and more claborate chip was designed at the University of North Carolina(U C) in cooperation with MCNC. Both VLSI chips had muliple datapaths for rule digital fuzzy inference chips had multiple datapaths for rule evaluation, and they executed multiple fuzzy if-then rules in parallel. The AT & T chip is the first digital fuzzy inference chip in the world. It ran with a 20 MHz clock cycle and achieved an approximately 80.000 Fuzzy Logical inferences Per Second (FLIPS). It stored and executed 16 fuzzy if-then rules. Since it was designed as a proof of concept prototype chip, it had minimal amount of peripheral logic for system integration. UNC/MCNC chip consists of 688,131 transistors of which 476,160 are used for RAM memory. It ran with a 10 MHz clock cycle. The chip has a 3-staged pipeline and initiates a computation of new inference every 64 cycle. This chip achieved an approximately 160,000 FLIPS. The new architecture have the following important improvements from the AT & T chip: Programmable rule set memory (RAM). On-chip fuzzification operation by a table lookup method. On-chip defuzzification operation by a centroid method. Reconfigurable architecture for processing two rule formats. RAM/datapath redundancy for higher yield It can store and execute 51 if-then rule of the following format: IF A and B and C and D Then Do E, and Then Do F. With this format, the chip takes four inputs and produces two outputs. By software reconfiguration, it can store and execute 102 if-then rules of the following simpler format using the same datapath: IF A and B Then Do E. With this format the chip takes two inputs and produces one outputs. We have built two VME-bus board systems based on this chip for Oak Ridge National Laboratory (ORNL). The board is now installed in a robot at ORNL. Researchers uses this board for experiment in autonomous robot navigation. The Fuzzy Logic system board places the Fuzzy chip into a VMEbus environment. High level C language functions hide the operational details of the board from the applications programme . The programmer treats rule memories and fuzzification function memories as local structures passed as parameters to the C functions. ASIC fuzzy inference hardware is extremely fast, but they are limited in generality. Many aspects of the design are limited or fixed. We have proposed to designing a are limited or fixed. We have proposed to designing a fuzzy information processor as an application specific processor using a quantitative approach. The quantitative approach was developed by RISC designers. In effect, we are interested in evaluating the effectiveness of a specialized RISC processor for fuzzy information processing. As the first step, we measured the possible speed-up of a fuzzy inference program based on if-then rules by an introduction of specialized instructions, i.e., min and max instructions. The minimum and maximum operations are heavily used in fuzzy logic applications as fuzzy intersection and union. We performed measurements using a MIPS R3000 as a base micropro essor. The initial result is encouraging. We can achieve as high as a 2.5 increase in inference speed if the R3000 had min and max instructions. Also, they are useful for speeding up other fuzzy operations such as bounded product and bounded sum. The embedded processor's main task is to control some device or process. It usually runs a single or a embedded processer to create an embedded processor for fuzzy control is very effective. Table I shows the measured speed of the inference by a MIPS R3000 microprocessor, a fictitious MIPS R3000 microprocessor with min and max instructions, and a UNC/MCNC ASIC fuzzy inference chip. The software that used on microprocessors is a simulator of the ASIC chip. The first row is the computation time in seconds of 6000 inferences using 51 rules where each fuzzy set is represented by an array of 64 elements. The second row is the time required to perform a single inference. The last row is the fuzzy logical inferences per second (FLIPS) measured for ach device. There is a large gap in run time between the ASIC and software approaches even if we resort to a specialized fuzzy microprocessor. As for design time and cost, these two approaches represent two extremes. An ASIC approach is extremely expensive. It is, therefore, an important research topic to design a specialized computing architecture for fuzzy applications that falls between these two extremes both in run time and design time/cost. TABLEI INFERENCE TIME BY 51 RULES {{{{Time }}{{MIPS R3000 }}{{ASIC }}{{Regular }}{{With min/mix }}{{6000 inference 1 inference FLIPS }}{{125s 20.8ms 48 }}{{49s 8.2ms 122 }}{{0.0038s 6.4㎲ 156,250 }} }}