• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.15 no.2
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• pp.89-94
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• 2022

In this paper, a discrete-time loop filter(DLF) phase-locked loop with a Frequency Fluctuation Converting Circuit(FFCC) has been proposed. Discrete-time loop filter can improve spur characteristic by connecting the charge pump and voltage oscillator discretely unlike a conventional continuous-time loop filter. The proposed PLL is designed to operate stably by the internal negative feedback loop including the SSC acting as a negative feedback to the discrete-time loop filter of the external negative feedback loop. In addition, the phase noise is further improved by reducing the magnitude of the loop filter output voltage variation through the FFCC. Therefore, the magnitude of jitter has been reduced by 1/3 compared to the conventional structure. The proposed phase locked loop has been simulated with Hspice using the 1.8V 180nm CMOS process.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.4
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• pp.241-246
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• 2007

This paper presents two novel compensation circuits for leakage current and power supply noise (PSN) in phase locked loop (PLL) using a nanometer CMOS technology. The leakage compensation circuit reduces the leakage current of the charge pump circuit and the PSN compensation circuit decreases the effect of power supply variation on the output frequency of VCO. The PLL design is based on a 32nm predictive CMOS technology and uses a 0.9 V power supply voltage. The simulation results show that the proposed PLL achieves 88% jitter reduction at 440 MHz output frequency compared to the PLL without leakage compensator and its output frequency drift is little to 20% power supply voltage variations. The PLL has an output frequency range of 40 $M{\sim}725$ MHz with a multiplication range of 1-1023, and the RMS and peak-to-peak jitter are 5psec and 42.7 psec, respectively.

• Journal of the Korea Institute of Military Science and Technology
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• v.15 no.4
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• pp.450-457
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• 2012

In this paper, we designed low phase noise frequency synthesizer with compact size for High frequency band (Ku-band). The paper addresses merits and demerits of single loop and dual loop frequency synthesizer. The phase noise characteristics of the phase-locked loop frequency synthesizer were predicted based on the analysis for phase noise contribution of noise sources. The proposed model in this paper more accurately predicts the low phase noise frequency synthesizer with compact size for high frequency band.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.53 no.7
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• pp.365-374
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• 2004

The relay measures the frequency of the power system in order to detect faults and separate them from the system. Many estimation algorithms for the relay have been proposed to accurately measure the frequency. This paper proposes a new frequency measurement method using the digital phase locked-loop(DPLL) for the relay of the power system. The proposed method is configured with a DPLL scheme and verified through computer simulations and experimental tests. In order to cope with noises in the power system, filters are included in the input signal processing part and the frequency comparator. MATLAB is used for computer simulations and an experimental setup with a CPU and an FPGA(Field Programmable Gate Array) is constructed. The loop filter of the DPLL is run in the CPU software In adjust parameters and others are in the FPGA. Experimental tests are performed lot a function generator and the power system. Results show that the proposed method is appropriate to the frequency measurement for the relay.

• Proceedings of the KIEE Conference
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• 2007.04a
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• pp.267-269
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• 2007

PLL(Phase Locked Loop) are widely used circuit technique in modern electronic systems. In this paper, We propose the low voltage and high speed PLL. We design the PFD(Phase Frequency Detector) by using TSPC (True Single Phase Clock) circuit to improve the performance and solve the dead-zone problem. We use CP(Charge Pump} and LP(Loop filter) for Negative feedback and current reusing in order to solve current mismatch and switch mismatch problem. The VCO(Voltage controlled Oscillator) with 5-stage differential ring oscillator is used to exact output frequency. The divider is implemented by using D-type flip flops asynchronous dividing. The frequency divider has a constant division ratio 32. The frequency range of VCO has from 200MHz to 1.1GHz and have 1.7GHz/v of voltage gain. The proposed PLL is designed by using 0.18um CMOS processor with 1.8V supply voltage. Oscillator's input frequency is 25MHz, VCO output frequency is 800MHz and lock time is 5us. It is evaluated by using cadence spectra RF tools.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.1643-1647
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• 2003

This paper, we propose a new high noise immunity phase-locked loop(PLL) which can suppress the high incident noise coupling with large amplitude and long period to the input frequency of PLL and keeps constant frequency and phase of the VCO output for providing the high stability distribution clock pulse.

• Proceedings of the KIEE Conference
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• 1987.11a
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• pp.86-89
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• 1987

This paper treats with the design and fabrication of a frequency synthesizer for the generation of intermediate frequency of a HF band transceiver. The synthesizer is designed to control frequencies using a phase-locked loop and it is shown that method improved the performance of frequency accuracy and locking time then that of the crystal-reference system.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.87-90
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• 2000

This paper describes a register-controlled symmetrical delay-locked-loop (DLL) using hybrid delay line for use in a high frequency double-data-rate DRAM. The proposed DLL uses a hybrid delay line which can cover two-step delays(coarse/fine delay) by one delay element. The DLL dissipate less power than a conventional dual-loop DLL which use a coarse and a fine delay element and control separately. Additionally, this DLL not only achieves small phase resolution compared to the conventional digital DLL's when it is locked but it also has a great simple delay line compared to a complex dual-loop DLL.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.6
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• pp.71-78
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• 1999

In this paper, a new model for optical phase-locked loop(OPLL) is proposed that includes VCO laser frequency response as well as loop propagation delay. It is found that both of them greatly affect the OPLL performance. Our model can be used for realizing high-performance microwave-range OPLL.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.12
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• pp.2933-2938
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• 2014

In this paper, the FLL(Frequency Locked Loop) circuit using current conveyor circuit is designed by $0.35{\mu}m$ CMOS process. The FLL circuit is built in a frequency divider, a frequency-to-voltage converter, a voltage subtractor and a oscillator and the circuit blocks have a symmetric structure to improve a reliability characteristics with a process variation. From the simulation results, the variation rate of output frequency is about less than ${\pm}1%$ when the channel length, channel width, resistance and capacitance are varied ${\pm}5%$.