• Journal of information and communication convergence engineering
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• 제7권1호
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• pp.62-65
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• 2009

In this paper, the temperature characteristics of full CMOS FLL(frequency locked loop) re analyzed. The FLL circuit is used to generate an output signal that tracks an input efference signal. The locking time of FLL is short compared to PLL(phase locked loop) circuit because the output signal of FLL is synchronized only in frequency. Also the FLL s designed to allow the circuit to be fully integrated. The FLL circuit is composed two VCs, two buffers, a VCO and two frequency dividers. The temperature variation of frequency divider, FVC and buffer cancelled because the circuit structure. is the same and he temperature effect is cancelled by the comparator. Simulation results are shown to illustrate the performance of the designed FLL circuit with temperature.

• Journal of information and communication convergence engineering
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• 제8권2호
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• pp.197-200
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• 2010

The FLL(frequency locked loop) circuit is used to generate an output signal that tracks an input reference signal. The locking time of FLL is short compared to PLL(phase locked loop) circuit because the output signal of FLL is synchronized only in frequency. Also the FLL is designed to allow the circuit to be fully integrated. In this paper, the temperature stable FLL circuit is designed by using full CMOS transistors. When the temperature is varied from $-20^{\circ}C$ to $70^{\circ}C$, the variation of output frequency is about from -2% to 1.6% from HSPICE simulation results.

• JSTS:Journal of Semiconductor Technology and Science
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• 제11권3호
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• pp.190-197
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• 2011

This paper presents a 144 GHz divide-by-2 injection locked frequency divider (ILFD) with inductive feedback developed in a commercial 90-nm Si RFCMOS technology. It was demonstrated that division-by-2 operation is achieved with input power down to -12 dBm, with measured locking range of 0.96 GHz (144.18 - 145.14 GHz) at input power of -3 dBm. To the authors' best knowledge, this is the highest operation frequency for ILFD based on a 90-nm CMOS technology. From supply voltage of 1.8 V, the circuit draws 5.7 mA including both core and buffer. The fabricated chip occupies 0.54 mm ${\times}$ 0.69 mm including the DC and RF pads.

• 전기학회논문지
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• 제63권12호
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• pp.1759-1763
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• 2014

In this paper, we were performed a structural analysis and durability analysis for an integral frame with an axle according to development of the electric locomotive traction motor. In terms of the structural stability, as a result of the analysis modeling with coupling conditions of beam element and an alternative element of three-dimensional, the maximum von-Mises stress of the locking screw mounting frame were similar as 50MPa and 51MPa. Also A comparison of the natural frequency and the exciting frequency while driving of the electric locomotive No. 8200, the natural frequency is 627.05Hz~856.9Hz while the exciting frequency is not more than most 30Hz or 553Hz, 1110Hz. Therefore, it is possible to avoid the resonance.

• 대한전자공학회논문지SD
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• 제47권12호
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• pp.75-82
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• 2010

본 논문은 다중대역 송수신기 CMOS RFIC 단일 칩을 위한 광대역 델타시그마 분수분주형 주파수합성기에 관한 것이다. 광대역 VCO의 LC Tank에 6-bit Switched Capacitor Array Bank를 작용하여 2340~3940 MHz의 출력주파수 범위를 가지도록 하였으며, 위상동기 전 Capacitor Bank Code를 선택하기위한 VCO Frequency Calibration 회로는 전체 주파수대역에서 $2{\mu}s$이하로 보정을 마치는 뛰어난 성능을 보여준다. 광대역 VCO로부터 T-DMB/DAB/FM Radio의 LO 신호를 생성하기 위해 선택 가능한 다중분주비 ${\div}2$, ${\div}16$, ${\div}32$를 가지는 LO 신호 발생기는 L-Band (1173 ~ 1973 MHz), VHF-III (147 ~ 246 MHz), VFH-II (74~123 MHz)에서 I/Q신호를 생성한다. Integrated Phase Noise는 전체 대역에서 0.8 degree RMS 이하로 측정되어 매우 낮은 위상잡음을 보여주었다. 또한, VCO Frequency Calibration 시간을 포함하는 주파수합성기의 전체 동기시간은 $50{\mu}s$ 이하로 측정되었다. 이 광대역 델타시그마 분수분주형 주파수합성기는 $0.13{\mu}m$ CMOS공정으로 제작되었으며, 1.2 V 전원전압에서 15.8 mA의 전류를 소모한다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권5호
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• pp.459-464
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• 2013

A reset-free anti-harmonic programmable multiplying delay-locked loop (MDLL) that provides flexible integer clock multiplication for high performance clocking applications is presented. The proposed MDLL removes harmonic locking problems by utilizing a simple harmonic lock detector and control logic, which allows this MDLL to change the input clock frequency and multiplication factor during operation without the use of start-up circuitry and external reset. A programmable voltage controlled delay line (VCDL) is utilized to achieve a wide operating frequency range from 80 MHz to 1.2 GHz with a multiplication factor of 4, 5, 8, 10, 16 and 20. This MDLL achieves a measured peak-to-peak jitter of 20 ps at 1.2 GHz.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2007년도 심포지엄 논문집 정보 및 제어부문
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• pp.286-288
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• 2007

In this paper, the fast locking PLL Frequency Synthesizer with low phase noise in a 0.18um CMOS process is presented. Its main application IS for the 915MHz ISM band wireless transponder upon the CPFSK (Continuous Phase Frequency Shift Keying) modulation scheme. Frequency synthesizer, which in this paper, is designed based on self-biased techniques and is independent with processing technology when damping factor and bandwidth fixed to most important parameters as operating frequency ratio, broad frequency range, and input phase offset cancellation. The proposed frequecy synthesizer, which is fully-integrated and is in 320M $^{\sim}$ 960MHz of the frequency range with 10MHz of frequency resolution. And its is implemented based on integer-N architecture. Its power consumption is 50mW at 1.8V of supply voltage and core area is $540{\mu}m$ ${\times}$ $450{\mu}m$. The measured phase noises are -117.92dBc/Hz at 10MHz offset, with low settling time less than $3.3{\mu}s$.

• 한국전자파학회논문지
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• 제22권3호
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• pp.399-405
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• 2011

본 논문에서는 130 nm RF CMOS 공정을 이용하여 77 GHz 자동차용 레이더 센서에 응용 가능한 Q-band LC 전압 제어 발진기(Voltage Controlled Oscillator: VCO)와 주입 잠금(injection locking) 버퍼를 설계한 결과를 보인다. LC 탱크의 위상 잡음 특성 개선을 위해 전송선을 이용하였고, 버퍼는 능동 소자 교차 결합쌍(cross-coupled pair)의 부성 저항(negative resistance)단을 이용해 발진 유무에 관계없이 높은 출력 전력을 가지도록 설계하였다. 측정된 위상 잡음은 1 MHz 오프셋 주파수에서 -102 dBc/Hz이며, 주파수 조정 범위는 34.53~35.07 GHz이다. 또한, 모든 주파수 조정 범위에서 출력 전력은 4.1 dBm 이상의 값을 가진다. 제작된 칩의 사이즈는 $510{\times}130\;um^2$이며, 1.2 V 바이어스 전압에서 LC 전압 제어 발진기가 10.8 mW, 주입 잠금 버퍼가 50.4 mW의 전력 소모를 가진다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 하계종합학술대회 논문집
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• pp.353-356
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• 1999

A 3.3V PLL(Phase Locked loop) is designed for a high frequency, low voltage, and low power applications. This paper proposes a new PLL architecture to improve voltage to frequency linearity of VCO(Voltage controlled oscillator) with new delay cell. The proposed VCO operates at a wide frequency range of 30MHz~1㎓ with a good linearity. The DC-DC voltage up/down converter is utilized to regulate the control voltage of the two-stage VCO. The designed PLL architecture is implemented on a 0.6${\mu}{\textrm}{m}$ n-well CMOS process. The simulation results show a locking time of 2.6$\mu$sec at 1Hz, Lock in range of 100MHz~1㎓, and a power dissipation of 112㎽.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 통신소사이어티 추계학술대회논문집
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• pp.86-89
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• 2003

In this paper, Self-Oscillating Mixer is designed by oscillator that was based on a general nonlinear input-output model for the subharmonic injection locked oscillator is analysed. We have designed and fabricated the Self-Oscillating Mixer for 5GHz by proposed subharmonic injection locked oscillator based frequency synthesizer structure that have characteristic of good frequency sensitivity, good phase noise. The design strategy leading to an optimized SILO with regards to its locking range is described and a test SOM circuit is demonstrated a 4dB conversion gain at 280MHz IF frequency from the carrier.