• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.3
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• pp.264-272
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• 2009

In this paper, a Ka-band 10 W power amplifier module is designed and fabricated using MIC(Microwave Integrated Circuit) module technology which combines multiple power MMIC(Monolithic Microwave Integrated Circuit) chips on a thin film substrate. Modified Wilkinson power dividers/combiners are used for millimeter wave modules and CBFGC-PW-Microstrip transitions are utilized for reducing connection loss and suppressing resonance in the high-gain and high-power modules. The power amplifier module consists of seven MMIC chips and operates in a pulsed mode. for the pulsed mode operation, a gate pulse control circuit supplying the control voltage pulses to MMIC chips is designed and applied. The fabricated power amplifier module shows a power gain of about 58 dB and a saturated output power of 39.6 dBm at a center frequency of the interested frequency band.

• Journal of Sensor Science and Technology
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• v.5 no.3
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• pp.9-16
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• 1996

This paper deals with the capacitive voltage divider which can measure a transient voltages generated by operating a high voltage impulse generator. The transient voltage measuring system using the capacitive electric field sensor consists of the planar-type electric field sensor having a fast response characteristic and the wide-bandwidth voltage follower, and the input impedance of which is extremely high, about $10^{12}{\Omega}$. In order to analyze the response characteristics to a step input, the newly developed calibration method is proposed, and the error of voltage dividing ratio associated with set-up condition is investigated. Also the optimal set-up condition that is to be maintained within the range of 0.5 % is taken. From the calibration experiment, the frequency bandwidth of the transient voltage measuring system whose response time to a step input is about 15.8 ns, is from 6.37 Hz to 27.3 MHz. Therefore it is possible to measure the commercial frequency voltages as well as the transient over voltages without signal distortions.

• Journal of Advanced Navigation Technology
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• v.24 no.6
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• pp.557-565
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• 2020

In order for thermal degradationIn, excore nuclear flux monitoring system, as a monitoring and signal processing methodology of reactor power, monitors neutron pulses generated during nuclear fission as frequency status, and converts them into DC voltage, and then log values resultantly. The methods realy applied in the nuclear power plant are to construct combination of counters and flip-flops, or diodes and capacitors up to now. These methodes are reliable for relative high frequencies, while not credible for reasonable low frequencies or extreme low values. Therefore, we developed the circuit that converts frequencies into DC voltages, into and into log DC values in the wide range from low Hz to several hundred high kHz. We proved their validities through testing them using real data used in nuclear power plant and analyzed their results. And, these methods will be used to measure the neutron level of excore nuclear flux monitoring system in nuclear power plant.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• v.2
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• pp.385-390
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• 2006

This paper examines the sampling and jitter specifications and considerations for Global Navigation Satellite Systems (GNSS) software receivers. Software radio (SWR) technologies are being used in the implementation of communication receivers in general and GNSS receivers in particular. With the advent of new GPS signals, and a range of new Galileo and GLONASS signals soon becoming available, GNSS is an application where SWR and software-defined radio (SDR) are likely to have an impact. The sampling process is critical for SWR receivers, where it occurs as close to the antenna as possible. One way to achieve this is by BandPass Sampling (BPS), which is an undersampling technique that exploits aliasing to perform downconversion. BPS enables removal of the IF stage in the radio receiver. The sampling frequency is a very important factor since it influences both receiver performance and implementation efficiency. However, the design of BPS can result in degradation of Signal-to-Noise Ratio (SNR) due to the out-of-band noise being aliased. Important to the specification of both the ADC and its clocking Phase- Locked Loop (PLL) is jitter. Contributing to the system jitter are the aperture jitter of the sample-and-hold switch at the input of ADC and the sampling-clock jitter. Aperture jitter effects have usually been modeled as additive noise, based on a sinusoidal input signal, and limits the achievable Signal-to-Noise Ratio (SNR). Jitter in the sampled signal has several sources: phase noise in the Voltage-Controlled Oscillator (VCO) within the sampling PLL, jitter introduced by variations in the period of the frequency divider used in the sampling PLL and cross-talk from the lock line running parallel to signal lines. Jitter in the sampling process directly acts to degrade the noise floor and selectivity of receiver. Choosing an appropriate VCO for a SWR system is not as simple as finding one with right oscillator frequency. Similarly, it is important to specify the right jitter performance for the ADC. In this paper, the allowable sampling frequencies are calculated and analyzed for the multiple frequency BPS software radio GNSS receivers. The SNR degradation due to jitter in a BPSK system is calculated and required jitter standard deviation allowable for each GNSS band of interest is evaluated. Furthermore, in this paper we have investigated the sources of jitter and a basic jitter budget is calculated that could assist in the design of multiple frequency SWR GNSS receivers. We examine different ADCs and PLLs available in the market and compare known performance with the calculated budget. The results obtained are therefore directly applicable to SWR GNSS receiver design.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.11
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• pp.9-16
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• 2005

This paper proposes a programmable PLL (phase locked loop) based clock generator supporting a wide-range-frequency input and output for high performance and low power SoC with multiple clock frequencies domains. The propose system reduces the locking time and obtains a wide range operation frequency by using a dual-charge pumps scheme. For low power operation of a chip, the locking processing circuits of the proposed PLL doesn't be working in the standby mode but the locking data are retained by the DAC. Also, a tracking ADC is designed for the fast relocking operation after stand-by mode exit. The programmable output frequency selection's circuit are designed for supporting a optimized DFS operation according to job tasks. The proposed PLL-based clock system has a relock time range of $0.85{\mu}sec{\sim}1.3{\mu}sec$($24\~26$cycle) with 2.3V power supply, which is fabricated on $0.35{\mu}m$ CMOS Process. At power-down mode, PLL power saves more than $95\%$ of locking mode. Also, the PLL using programmable divider has a wide locking range ($81MHz\~556MHz$) for various clock domains on a multiple IPs system.

• Journal of Advanced Navigation Technology
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• v.15 no.1
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• pp.97-103
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• 2011

This paper presents a dual-band balanced mixer using nonlinear phase characteristic of composite right/left-handed (CRLH) transmission line. This metamaterial structure provides low LO leakage and high RF to LO isolation without additional filters for LO and RF path. The balanced mixer consists of balun and Wilkinson divider with dual-band characteristic of unit-cell which behaves like a CRLH metamaterial. Experimental results are used to verify the proposed metamaterial functions. The balanced mixer design results in an operating frequency of 870 MHz and 1660 MHz with an optimum mixer conversion loss of 15.2 dB at 870 MHz and 21.2 dB at 1660 MHz.

• Journal of Advanced Navigation Technology
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• v.21 no.1
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• pp.66-71
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• 2017

This paper describes implementation of a 165 MHz, 5 kW RF high power amplifier (HPA) for particle accelerator applications. The HPA consists of a drive amplifier for main amplifiers driving, sixteen 600 W class-AB push-pull power amplifier pallets and Wilkinson power divider/combiner using lumped LC components, which are divided/combined power amplifier pallet outputs. To detected the amplifier circuit of normal and reflected output power conditions, we used a bidirectional coupler. To radiate heat of main power amplifier, we were used an water-cooled copper plates to go through a water for radiation of heat. The HPA of center frequency 165 MHz has archived an efficiency of 62.5 % at 5 kW of power level experimentally.

• Journal of the Korean Applied Science and Technology
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• v.36 no.4
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• pp.1410-1419
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• 2019

In this research, it is to find a method that frost does not form on the outdoor unit to develop a heat pump capable of heating in cold regions. For this reason, we produced an incubator capable of creating an environment of -25℃, and constructed an experimental apparatus so that experiments in the room were possible. However, it is necessary to grasp the characteristics of the air reaching the front of the heat pump outdoor unit installed in the experimental apparatus, and flow analysis was performed using ANSYS CFX, which is general-purpose software. As a result, the flow velocity of the air reaching the front of the outdoor unit in the outdoor unit chamber in the entire region of the simulation conditions (5.0 to 7.5 m/s) has many differences in the upper and lower portions, resulting in a natural state. It turned out that the condition can not be satisfied. Therefore, it is determined that it is necessary to additionally install a frequency divider at the front of the outdoor unit to make the flow velocity constant.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.5
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• pp.99-105
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• 2014

A reference spur suppressed PLL with two-symmetrical loops without changing the bandwidth which is optimized to suppress phase noise and reduce locking time has been designed. The principle of suppressing a reference signal spur is to stabilize the input voltage of voltage controlled oscillator (VCO). The proposed PLL consists of a phase-frequency detector(PFD) which has two outputs, two charge pumps(CP), two loop filters(LF), a divider and a VCO which has two inputs. Simulation results with $0.18{\mu}m$ CMOS process show that the reference spur is approximately suppressed to 1/2 of the reference spur in a conventional PLL. Even though there is a 5% process variation in the magnitude of R and C, the simulation result shows that the reference spur is still suppressed to 1/2 of the reference spur in a conventional PLL. The power consumption is 6.3mW at the power supply of 1.8V.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.5C
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• pp.506-511
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• 2002

In this paper, waveguide-based power combiner using conventional slotline-to-microstrip transition was proposed at Ka-band. The proposed 2-way and 4-way power combiner consist of waveguide-to-slotline transition, two or four slotline-to-microstrip transitions, and impedance matching networks. Their structures were simulated and optimized by 3-D FEM simulation. The 2-way power combiner showed a very low back-to-back insertion loss of 1.0 dB and return loss better than 15 dB from 25.7 GHz to 29.8 GHz except the resonant frequency. The 2-way power combining approach was extended to 4-way power combining using slotline tee junction. The 4-way power combiner showed the similar performance to that of 2-way power combiner with 2 GHz smaller bandwidth.