• Journal of Biomedical Engineering Research
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• v.25 no.6
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• pp.611-615
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• 2004

A neural prostheses can be designed to permit stimulation of specific sites in the nervous system to restore their functions, lost due to disease or trauma. This study focuses on the feasibility of optoelecronic stimulation into nervous system. Optoelectronic stimulation supplies, power and signal into the implanted optical detector inside the body by optics. It can be effective strategy especially on the retinal prosthesis, because it enables the non-invasive connection between the external source and internal detector through natural optical window 'eye'. Therefore, we designed an effective neural stimulating setup by optically based stimulation. Stimulating on the sciatic nerve of a rat with proper depth probe through optical stimulation needs higher ratio of current spreading through the neural surface, because of high impedance of neural interface. To increase the insertion current spreading into the neuron, we used a parallel low resistance compared to load resistance organic interface and calculated the optimized outer parallel resistance for maximum insertion current with the assumption of limited current by photodiode. Optimized outer parallel resistance was at a range of 500Ω-700Ω and a current was at a level between 580uA and 650uA. Stimulating current efficiency from initial photodiode induced current was between 47.5 and 59.7%. Various amplitude and frequency of the optical stimulation on the sciatic nerve showed the reliable visual tremble, and the action potential was also recorded near the stimulating area. These result demonstrate that optoelectronic stimulation with no bias can be applied to the retinal prosthesis and other neuroprosthetic area.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.5
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• pp.359-369
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• 2020

In this paper, we proposed a charge pump (CP) circuit that has a wide operating range while reducing the current mismatch for the PLL that generates the main clock of the CMOS X-Ray detector. The operating range and current mismatch of the CP circuit are determined by the characteristics of the current source circuit for the CP circuit. The proposed CP circuit is implemented with a wide operating current mirror bias circuit to secure a wide operating range and a cascode structure with a large output resistance to reduce current mismatch. The proposed wide operating range cascode CP circuit was fabricated as a chip using a 350nm CMOS process, and current matching characteristics were measured using a source measurement unit. At this time, the power supply voltage was 3.3 V and the CP circuit current ICP = 100 ㎂. The operating range of the proposed CP circuit is △VO_Swing=2.7V, and the maximum current mismatch is 5.15 % and the maximum current deviation is 2.64 %. The proposed CP circuit has low current mismatch characteristics and can cope with a wide frequency range, so it can be applied to systems requiring various clock speed.

• Korean Journal of Optics and Photonics
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• v.2 no.3
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• pp.139-148
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• 1991

A fiber-optic magnetic sensor system for the detection of small ac magnetic field(200Hz-2 kHz) was constructed. Magnetic field sensing part was fabricated by bonding a section of optical fiber to amorphous metallic glass(2605SC) having large magnetostriction effect. And with the directional coupler, all fiber type Mach-Zehnder interferometer was constructed to measure the variation of the external magnetic field by translating it into the optical phase shift in the interferometer. The signal fading problem of the interferometer, which is due to random phase drifts originated from the environment, i.e., temperature fluctuation, vibrations, etc., was elliminated by feedback phase compensation. This allows the sensitivity to be maintained at the maximum by keeping the interferometer in quadrature phase condition. The frequency response of metallic glass was found to be nearly flat in the range of 90 Hz-2 kHz and dc bias field for the maximum ac response was 3.5 Oe. The interferometer output showed good linearity over the range $\pm$0.5 Oe. For 1 kHz ac magnetic field the scale factor S and the minimum detectable magnetic field were measured to be 8.0 rad/Oe and $3X10^{-6} Oe/\sqrt{Hz}$at 1 Hz detection bandwidth respectively.

• The Journal of the Korea institute of electronic communication sciences
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• v.14 no.2
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• pp.309-316
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• 2019

In this paper, a low-jitter delay-locked loop that compensates for local clock skew is presented. The proposed DLL consists of a phase splitter, a phase detector(PD), a charge pump, a bias generator, a voltage-controlled delay line(VCDL), and a level converter. The VCDL uses self-biased delay cells using current mode logic(CML) to have insensitive characteristics to temperature and supply noises. The phase splitter generates two reference clocks which are used as the differential inputs of the VCDL. The PD uses the only single clock from the phase splitter because the PD in the proposed circuit uses CMOS logic that consumes less power compared to CML. Therefore, the output of the VCDL is also converted to the rail-to-rail signal by the level converter for the PD as well as the local clock distribution circuit. The proposed circuit has been designed with a $0.13-{\mu}m$ CMOS process. A global CLK with a frequency of 1-GHz is externally applied to the circuit. As a result, after about 19 cycles, the proposed DLL is locked at a point that the control voltage is 597.83mV with the jitter of 1.05ps.

• Atmosphere
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• v.31 no.5
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• pp.607-623
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• 2021

This study presents projections of future extreme climate over the Korean Peninsula (KP), using bias-corrected data from multiple regional climate model (RCM) simulations in CORDEX-EA Phase 2 project. In order to confirm difference according to degree of greenhouse gas (GHG) emission, high GHG path of SSP5-8.5 and low GHG path of SSP1-2.6 scenario are used. Under SSP5-8.5 scenario, mean temperature and precipitation over KP are projected to increase by 6.38℃ and 20.56%, respectively, in 2081~2100 years compared to 1995~2014 years. Projected changes in extreme climate suggest that intensity indices of extreme temperatures would increase by 6.41℃ to 8.18℃ and precipitation by 24.75% to 33.74%, being bigger increase than their mean values. Both of frequency indices of the extreme climate and consecutive indices of extreme precipitation are also projected to increase. But the projected changes in extreme indices vary regionally. Under SSP1-2.6 scenario, the extreme climate indices would increase less than SSP5-8.5 scenario. In other words, temperature (precipitation) intensity indices would increase 2.63℃ to 3.12℃ (14.09% to 16.07%). And there is expected to be relationship between mean precipitation and warming, which mean precipitation would increase as warming with bigger relationship in northern KP (4.08% ℃^-1) than southern KP (3.53% ℃^-1) under SSP5-8.5 scenario. The projected relationship, however, is not significant for extreme precipitation. It seems because of complex characteristics of extreme precipitation from summer monsoon and typhoon over KP.

• The Journal of the Acoustical Society of Korea
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• v.28 no.1
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• pp.77-83
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• 2009

This paper proposes a new noise-biased compensation of minimum statistics(MS) method using a nonlinear function and a priori speech absence probability(SAP) for speech enhancement in non-stationary noisy environments. The minimum statistics(MS) method is well known technique for noise power estimation in non-stationary noisy environments. It tends to bias the noise estimate below that of true noise level. The proposed method is combined with an adaptive parameter based on a sigmoid function and a priori speech absence probability (SAP) for biased compensation. Specifically. we apply the adaptive parameter according to the a posteriori SNR. In addition, when the a priori SAP equals unity, the adaptive biased compensation factor separately increases ${\delta}_{max}$ each frequency bin, and vice versa. We evaluate the estimation of noise power capability in highly non-stationary and various noise environments, the improvement in the segmental signal-to-noise ratio (SNR), and the Itakura-Saito Distortion Measure (ISDM) integrated into a spectral subtraction (SS). The results shows that our proposed method is superior to the conventional MS approach.

• Journal of Korea Water Resources Association
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• v.57 no.9
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• pp.571-583
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• 2024

Forecasting dam inflows in the medium to long term is crucial for effective dam operation and the prevention of water-related disasters such as floods and droughts. However, the increasing frequency of extreme weather events due to climate change has made hydrological forecasting more challenging. Since 2000, seasonal weather forecasts, which provide predictions for weather variables up to about seven months ahead, and their hydrological interpretation, known as Seasonal Flow Forecasts (SFFs) have gained significant global interest. This study utilises seasonal weather forecasts from the European Centre for Medium-Range Weather Forecasts (ECMWF), converting them into inflow forecasts using a hydrological model for 12 multipurpose dams in South Korea from 2011 to 2020. We then compare the performance of these SFFs with the Ensemble Streamflow Prediction (ESP). Our results indicate that while SFFs are more effective for short-term predictions of 1-2 months, ESP outperforms SFFs for long-term predictions. Seasonally, the performance of SFFs is higher in October-November but lower from December to February. Moreover, our findings demonstrate that SFFs are highly effective in quantitatively predicting dry conditions, although they tend to underestimate inflows under wet conditions.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.3
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• pp.46-55
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• 2016

This work proposes a 13b 100MS/s 45nm CMOS ADC with a high dynamic performance for IF-domain high-speed signal processing systems based on a four-step pipeline architecture to optimize operating specifications. The SHA employs a wideband high-speed sampling network properly to process high-frequency input signals exceeding a sampling frequency. The SHA and MDACs adopt a two-stage amplifier with a gain-boosting technique to obtain the required high DC gain and the wide signal-swing range, while the amplifier and bias circuits use the same unit-size devices repeatedly to minimize device mismatch. Furthermore, a separate analog power supply voltage for on-chip current and voltage references minimizes performance degradation caused by the undesired noise and interference from adjacent functional blocks during high-speed operation. The proposed ADC occupies an active die area of $0.70mm^2$, based on various process-insensitive layout techniques to minimize the physical process imperfection effects. The prototype ADC in a 45nm CMOS demonstrates a measured DNL and INL within 0.77LSB and 1.57LSB, with a maximum SNDR and SFDR of 64.2dB and 78.4dB at 100MS/s, respectively. The ADC is implemented with long-channel devices rather than minimum channel-length devices available in this CMOS technology to process a wide input range of $2.0V_{PP}$ for the required system and to obtain a high dynamic performance at IF-domain input signal bands. The ADC consumes 425.0mW with a single analog voltage of 2.5V and two digital voltages of 2.5V and 1.1V.

• Journal of fish pathology
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• v.6 no.2
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• pp.111-122
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• 1993

The mechanism by which $V_H$ region gene segments is selected in B lymphocyte is not known. Moreover, evidence for both random and nonrandom expression of $V_H$ genes in matured B cells has been presented previously. In this report, the technique of in situ hybridization allowed us to analyze expressed $V_H$ gene families in normal B lymphocyte at the single cell level. The analysis of normal B cells in this study eliminated any posssible bias resulting from transformation protocols used previously and minimized limitation associated with sampling size. Therefore, an accurate measure of the functional and expressed $V_H$ gene repertoire in B lymphocyte could be made. One of the most important controls for the optimization of in situ hybridization is to establish probe concentration and washing stringency due to the degree of nucleotide sequence similarlity between different families which in some cases can be as high as 70%. When the radioactive $C{\mu}$ and $V_{H}J558$ RNA probes are tested on LPS-stimulated adult spleen cells, $2{\sim}4{\times}106cpm$/slide shows low background and reasonable frequency of specific positive cells. For the washing condition. 40~50% formamide at $54^{\circ}C$ is found to be optimum for the $C{\mu}$. $V_{H}S107$ and $V_{H}J558$ probes. The analyzed results clearly demonstrate that the level of each different $V_H$ gene family expression is dependent upon the complexity or size of that family. These findings are also extended to the level of $V_H$ gene family expression in separated bone marrow B cells depend upon the various stage of differentiation and conclude no preferential utilization of specific $V_H$ gene family. Thus, the utilization of VH gene segments in B lymphocyte of adult BALB/c mice is random and is not regulated or changed during the differentiation of B cells.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.60-68
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• 2009

This work proposes a 10b 200MS/s 65nm CMOS ADC for high-definition video systems such as HDTV requiring high resolution and fast operating speed simultaneously. The proposed ADC employs a four-step pipeline architecture to minimize power consumption and chip area. The input SHA based on four capacitors reduces the output signal range from $1.4V_{p-p}$ to $1.0V_{p-p}$ considering high input signal levels at a low supply voltage of 1.2V. The proposed three-stage amplifiers in the input SHA and MDAC1 overcome the low output resistance problem as commonly observed in a 65nm CMOS process. The proposed multipath frequency-compensation technique enables the conventional RNMC based three-stage amplifiers to achieve a stable operation at a high sampling rate of 200MS/s. The conventional switched-bias power-reduction technique in the sub-ranging flash ADCs further reduces power consumption while the reference generator integrated on chip with optional off-chip reference voltages allows versatile system a locations. The prototype ADC in a 65nm CMOS technology demonstrates a measured DNL and INL within 0.19LSB and 0.61LSB, respectively. The ADC shows a maximum SNDR of 54.BdB and 52.4dB and a maximum SFDR of 72.9dB and 64.8dB at 150MS/S and 200MS/s, respectively. The proposed ADC occupies an active die area of $0.76mm^2$ and consumes 75.6mW at a 1.2V supply voltage.