• Proceedings of the KAIS Fall Conference
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• 2003.06a
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• pp.267-270
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• 2003

All artificial infernal organs which are using electric energy supply energy with inductive couple. Transcutaneous energy transmission system enhance survival chance of the patients and quality of life by reducing volume and mass. In this research, we used both tune in transmission system in state of fixing cycle in order to increase the voltage gain and the current gain and to reduce effect of leakage inductance. Also to maximize the effect of resonance, a constant frequency duty cycle control method is used. Test is progressed with litz wire which is set up with various sizes of core to minimize size of converter. This research aimed in analysis of transcutaneous energy transmission system and in measuring of stability and efficiency of Lithium-ion battery charge which are using transmitted energy.

• Journal of Power Electronics
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• v.19 no.1
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• pp.1-10
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• 2019

Current imbalance is the main factor affecting the lifespan of light-emitting diode (LED) lighting systems and is generally solved by active or passive approaches. Given many new lighting applications, independent control is particularly important in achieving different levels of luminance. Existing passive and active approaches have their own limitations in current sharing and independent control, which bring new challenges to the design of LED drivers. In this work, a multichannel resonant converter based on switched-capacitor control (SCC) is proposed for solving this challenge. In the resonant network of the upper and lower half-bridges, SCC is used instead of fixed capacitance. Then, the individual current of the LED array is obtained through regulation of the effective capacitance of the SCC under a fixed switching frequency. In this manner, the complexity of the control unit of the circuit and the precision of the multichannel outputs are further improved. Finally, the superior performance of the proposed LED driver is verified by simulations and a 4-channel experimental prototype with a rated output power of 20 W.

• Proceedings of the KIPE Conference
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• 2020.08a
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• pp.369-370
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• 2020

본 논문에서는 전기자동차용 양방향 배터리 충전장치에 사용되는 CHFL(Cycloconverter-type High Frequency Link) 컨버터에서 발생하는 고전압 스파이크 저감을 위한 스위칭 방법을 제안한다. CHFL 컨버터는 양극성 고주파 파형 정류시 LC 필터의 인덕터와 변압기의 누설 인덕터에 저장된 에너지로 인해 고전압 스파이크가 발생하게 된다. 제안된 스위칭 방법은 환류 구간을 통해 저장된 에너지를 회생시킴으로서 고전압 스파이크 문제를 해결할 수 있다. 제안된 스위칭 방법의 성능은 MATLAB/ Simulink 시뮬레이션을 통해 검증하였다.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.15 no.5
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• pp.335-342
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• 2022

In this paper, a single-bit 3rd-order feedforward delta sigma modulator is proposed for audio applications. The proposed modulator is based on a class-C inverter for low voltage and power applications. For the high-precision requirement, the class-C inverter with regulated cascode structure increases its DC gain and acts as a low-voltage subthreshold amplifier. The proposed Class-C inverter-based modulator is designed and simulated in 180-nm CMOS process. With no performance loss and a low supply voltage compatibility, the proposed class-C inverter-based switched-capacitor modulator achieves high power efficiency. This design achieves an signal-to-noise-and-distortion ratio (SNDR) of 93.9 dB, an signal-to-noise ratio (SNR) of 108 dB, an spurious-free dynamic range (SFDR) of 102 dB, and a dynamic range (DR) of 102 dB at a signal bandwidth of 20 kHz and a sampling frequency of 4 MHz, while only using 280 μW of power consumption from a 0.8-V power supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.10
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• pp.45-52
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• 2008

We investigated the design of an RF-powered, wireless temperature sensor tag chip using $0.18-{\mu}m$ CMOS technology. The transponder generates its own power supply from small incident RF signal using Schottky diodes in voltage multiplier. Ambient temperature is measured using a new low-power temperature-to-voltage converter, and an 8-bit single-slope ADC converts the measured voltage to digital data. ASK demodulator and digital control are combined to identify unique transponder (ID) sent by base station for multi-transponder applications. The measurement of the temperature sensor tag chip showed a resolution of $0.64^{\circ}C/LSB$ in the range from $20^{\circ}C$ to $100^{\circ}C$, which is suitable for environmental temperature monitoring. The chip size is $1.1{\times}0.34mm^2$, and operates at clock frequency of 100 kHz while consuming $64{\mu}W$ power. The temperature sensor required a -11 dBm RF input power, supported a conversion rate of 12.5 k-samples/sec, and a maximum error of $0.5^{\circ}C$.

• The Journal of the Korea institute of electronic communication sciences
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• v.14 no.2
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• pp.309-316
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• 2019

In this paper, a low-jitter delay-locked loop that compensates for local clock skew is presented. The proposed DLL consists of a phase splitter, a phase detector(PD), a charge pump, a bias generator, a voltage-controlled delay line(VCDL), and a level converter. The VCDL uses self-biased delay cells using current mode logic(CML) to have insensitive characteristics to temperature and supply noises. The phase splitter generates two reference clocks which are used as the differential inputs of the VCDL. The PD uses the only single clock from the phase splitter because the PD in the proposed circuit uses CMOS logic that consumes less power compared to CML. Therefore, the output of the VCDL is also converted to the rail-to-rail signal by the level converter for the PD as well as the local clock distribution circuit. The proposed circuit has been designed with a $0.13-{\mu}m$ CMOS process. A global CLK with a frequency of 1-GHz is externally applied to the circuit. As a result, after about 19 cycles, the proposed DLL is locked at a point that the control voltage is 597.83mV with the jitter of 1.05ps.

• Journal of Power Electronics
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• v.14 no.6
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• pp.1100-1108
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• 2014

Modular multilevel converters (MMCs) have emerged as the most promising topology for high and medium voltage applications for the coming years. However, one particular negative characteristic of MMCs is the existence of circulating current, which contains a dc component and a series of low-frequency even-order ac harmonics. If not suppressed, these ac harmonics will distort the arm currents, increase the power loses, and cause higher current stresses on the semiconductor devices. Repetitive control (RC) is well known due to its distinctive capabilities in tracking periodic signals and eliminating periodic errors. In this paper, a novel circulating current control scheme base on RC is proposed to effectively track the dc component and to restrain the low-frequency ac harmonics. The integrating function is inherently embedded in the RC controller. Therefore, the proposed circulating current control only parallels the RC controller with a proportional controller. Thus, conflicts between the RC controller and the traditional proportional integral (PI) controller can be avoided. The design methodologies of the RC controller and a stability analysis are also introduced. The validity of the proposed circulating current control approach has been verified by simulation and experimental results based on a three-phase MMC downscaled prototype.

• Journal of Power Electronics
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• v.13 no.6
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• pp.1058-1069
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• 2013

This paper proposes and designs a new output filter called an LCFL filter for application to three phase three wire shunt active power filters (SAPF). This LCFL filter is derived from a traditional LCL filter by replacing its capacitor with a C-type filter, and then constructing an L-C-type Filter-L (LCFL) topology. The LCFL filter can provide better switching ripple attenuation capability than traditional passive damped LCL filters. The LC branch series resonant frequency of the LCFL filter is set at the switching frequency, which can bypass most of the switching harmonic current generated by a SAPF converter. As a result, the power losses in the damping resistor of the LCFL filter can be reduced when compared to traditional passive damped LCL filters. The principle and parameter design of the LCFL filter are presented in this paper, as well as a comparison to traditional passive damped LCL filters. Simulation and experimental results are presented to validate the theoretical analyses and effectiveness of the LCFL filter.

• The Transactions of the Korea Information Processing Society
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• v.7 no.1
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• pp.235-244
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• 2000

This paper presents a low power PLL based clock geneator circuit for microprocessors. It generates 32MHz${\sim}$1GHz clocks and can be integrated inside microprocessor chips. A high speed D Flip-Flop is designed using dynamic differential latch and a new Phase Frequency Detector(PFD) based on this FF is presented. The PFD enjoys low error characteristics in phase sensitivity and the PLL using this PFD has a low phase error. To improve the linearity of voltage controlled oscillator(VCO) in PLL, the voltage to current converter and current controlled oscillator combination is suggested. The resulting PLL provides wide lock range and extends frequency of generated clocks over 1 GHz. The clock generator is designed by using $0.65\;{\mu}m$ CMOS full custom technology and operates with $11\;{\mu}s$ lock-in time. The power consumption is less than 20mW.

• Journal of IKEEE
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• v.13 no.4
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• pp.63-68
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• 2009

The power management integrated circuit(PMIC) for CCD image sensor is presented in this study. A CCD image sensor is very sensitive against temperature. The temperature, that is heat, is generally generated by the PMIC with low efficiency. Since the generated heat influences performance of CCD image sensor, it should be minimized by using a PMIC which has a high efficiency. In order to develop the PMIC with high efficiency, the input stage is designed with synchronous type step down DC-DC converter. The operating range of the converter is from 5V to 15V and the converter is controlled using PWM method. The PWM control circuit consists of a saw-tooth generator, a band-gap reference circuit, an error amplifier and a comparator circuit. The saw-tooth generator is designed with 1.2MHz oscillation frequency. The comparator is designed with the two stages OP Amp. And the error amplifier has 40dB DC gain and $77^{\circ}$ phase margin. The output of the step down converter is connected to input stage of the charge pump. The output of the charge pump is connected to input of the LDO which is the output stage of the PMIC. Finally, the PMIC, based on the PWM control circuit and the charge pump and the LDO, has output voltage of 15V, -7.5V, 3.3V and 5V. The PMIC is designed with a 0.35um process.