• Journal of Power Electronics
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• v.18 no.5
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• pp.1523-1535
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• 2018

High-performance Phase-Locked Loops (PLLs) are critical for grid synchronization in grid-tied power electronic applications. In this paper, a new single-phase All Digital Phase-Locked Loop (ADPLL) is proposed. It features fast transient response and good robustness under distorted grid conditions. It is designed for Field Programmable Gate Array (FPGA) implementation. As a result, a high sampling frequency of 1MHz can be obtained. In addition, a new OSG is adopted to track the power frequency, improve the harmonic rejection and remove the dc offset. Unlike previous methods, it avoids extra feedback loop, which results in an enlarged system bandwidth, enhanced stability and improved dynamic performance. In this case, a new parameter optimization method with consideration of loop delay is employed to achieve a fast dynamic response and guarantee accuracy. The Phase Detector (PD) and Voltage Controlled Oscillator (VCO) are realized by a Coordinate Rotation Digital Computer (CORDIC) algorithm and a Direct Digital Synthesis (DDS) block, respectively. The whole PLL system is finally produced on a FPGA. A theoretical analysis and experiments under various distorted grid conditions, including voltage sag, phase jump, frequency step, harmonics distortion, dc offset and combined disturbances, are also presented to verify the fast dynamic response and good robustness of the ADPLL.

• Proceedings of the KIPE Conference
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• 2017.11a
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• pp.7-8
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• 2017

The Phase-Locked Loop (PLL) is widely used in grid-tie inverter applications to achieve the synchronization between the inverter and the grid. However, its performance is deteriorated when the grid voltage is not pure sinusoidal due to the harmonics and the frequency deviation. Therefore it is important to design a high performance phase-locked loop (PLL) for the single phase inverter applications to guarantee the quality of the inverter output. In this paper a simple method to improve the performance of the PLL for the single phase inverter is proposed. The proposed PLL is able to accurately estimate the fundamental frequency component of the grid voltage even in the presence of harmonic components. In additional its transient response is fast enough to track a change in grid voltage within two cycles of the fundamental frequency. The effectiveness of the proposed PLL is confirmed through the PSIM simulation and experiments.

• Proceedings of the KIPE Conference
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• 2018.11a
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• pp.104-106
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• 2018

The harmonics and the DC offset in the grid can cause serious synchronization problems for grid connected inverters (GCIs) which leads not able to satisfy the IEEE 519 and p1547 standards in terms of phase and frequency variations. In order to guarantee the smooth and reliable synchronization of GCIs with the grid, Phase Locked Loop (PLL) is the crucial element. Typically, the performance of the PLL is assessed to limit the grid disturbances e.g. grid harmonics, DC Offset and voltage sag etc. To ensure the quality of GCI, the PLL should be precise in estimating the grid amplitude, frequency and phase. Therefore, in this paper a novel Robust PLL technique called Digital Lock-in Amplifier (DLA) PLL is proposed. The proposed PLL estimate the frequency variations and phase errors accurately even in the highly distorted grid voltage conditions like grid voltage harmonics, DC offsets and grid voltage sag. To verify the performance of proposed method, it is compared with other six conventional used PLLs (CCF PLL, SOGI PLL, SOGI LPF PLL, APF PLL, dqDSC PLL, MAF PLL). The comparison is done by simulations on MATLAB Simulink. Finally, the experimental results are verified with Single Phase GCI Prototype.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.6
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• pp.290-297
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• 2014

The synchronization of OFDM receiver is consisted of symbol timing offset(STO) estimation in time domain and carrier frequency offset(CFO) estimation in frequency domain. This paper proposes new algorithm for correcting the integer CFO after we have done correcting the STO and partial CFO. ICFO must be corrected, since the ICFO lead to degrade bit error rate(BER) of demodulation performance. The PN sequence has information which is subcarrier order since the modified PN sequence, length is same subcarrier, is used in this paper and is modulated each subcarrier by each chip. Thus the receiver track phase of PN sequence after FFTin order to find the subcarrier frequency offset. The proposed algorithm is faster and more simple than convenient methode as measuring carrier energy.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.44 no.3
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• pp.266-273
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• 2016

In this paper, we propose the signal processing techniques for the command link receiver mounted to aircrafts flying at a high speed. In order to acquire the various information transmitted from ground through radio frequency links, the wide received signal range must be guaranteed as well as the carrier synchronization and symbol synchronization be performed correctly within short pulse sections. After the synchronization step, we should be able to achieve theoretical performance of the modulation and demodulation scheme applied as deciding bit and symbol at the time appointed. By test results, we make sure that the proposed signal processing techniques can be effectively applied command link receiver mounted to aircrafts.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 1995.06a
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• pp.63-67
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• 1995

This paper proposes a new frequency offset correction technique for OFDM receivers on a frequency-selective fading channel. The frequency offset in the OFDM signals is known to introduce an interchannel interference among the multiple subcarriers, which degrades the receiver performance severely. In order to reduce the frequency offset, this paper describes an algorithm with two stages: acquisition and tracking. At both stages the algorithm oversamples the received OFDM signals. At the acquisition stage the frequency offset is reduced to half or less than the intercarrier spacing by matching the sign patterns of even and odd samples. Next, at tracking stage the frequency offset is compensated by a frequency detector which is controlled by the correlation of the even and odd sample sets. From the results, it is found that the proposed algorithm can correct the frequency offset even if the initial offset exceeds one half of th eintercairrers spacing.

• The Journal of the Acoustical Society of Korea
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• v.38 no.2
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• pp.154-159
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• 2019

When measuring the radiating noise of an underwater moving source, the range information between the acoustic source and the receiver is an important evaluation factor, and the measurement standards such as a receiver position, a moving source depth and a speed are set. Although there is a method of using the cross correlation as a method of finding the range of the underwater moving source, this method requires a time synchronization process. In this paper, we proposed the method to estimate the range by comparing the Doppler frequency difference of the theoretically calculated multipath signal with the Doppler frequency difference of the multipath signal estimated from the received signal. The proposed method does not require a separate time synchronization process. Simulations were performed to verify the performance, and the ranging error of the proposed method reduced by about 95 % than that of the conventional method.

• Journal of Positioning, Navigation, and Timing
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• v.13 no.1
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• pp.111-115
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• 2024

This study builds a machine learning model optimized for clocks among various techniques in the field of artificial intelligence and applies it to clock stabilization or synchronization technology based on atomic clock noise characteristics. In addition, the possibility of providing stable source clock data is confirmed through the characteristics of machine learning predicted values during holdover of atomic clocks. The proposed machine learning model is evaluated by comparing its performance with the AutoRegressive Integrated Moving Average (ARIMA) model, an existing statistical clock prediction model. From the results of the analysis, the prediction model proposed in this study (MSE: 9.47476) has a lower MSE value than the ARIMA model (MSE: 221.2622), which means that it provides more accurate predictions. The prediction accuracy is based on understanding the complex nature of data that changes over time and how well the model reflects this. The application of a machine learning prediction model can be seen as a way to overcome the limitations of the statistical-based ARIMA model in time series prediction and achieve improved prediction performance.

• Journal of IKEEE
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• v.17 no.3
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• pp.248-253
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• 2013

Frequency detector is a circuit that converts the frequency to a digital representation and finds its application in various fields such as modulator and synchronization circuitry. In this paper, a couple of first-order and second-order frequency discriminator structures are modeled and analyzed with their quantization noise sources. Also a delta-sigma frequency detector architecture is proposed. Through theoretical analysis and derived equations, the output noise is obtained, which is validated by simulation. The proposed all-digital frequency discriminator may be applied in the feedback path of the all-digital phase-locked loop.

• ETRI Journal
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• v.24 no.3
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• pp.247-250
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• 2002

In this paper, we propose three symbol syn-chronization schemes for Orthogonal Frequency Division Multiplex (OFDM) systems. The cyclic extension preceding OFDM symbols is of decisive importance for these schemes. The first scheme uses the phase-differential coding of the received OFDM signal. The second and the third schemes use the length of the received OFDM signal. All three schemes make symbol synchronization possible, even though there is a frequency off-set in the system. Simulation results show that these schemes can be used to synchronize an OFDM system over AWGN and multi-path fading channels.