• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.29 no.11
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• pp.842-850
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• 2018

In this paper, the design and fabrication of a frequency-locked-loop(FLL) 5-GHz oscillator with a single resonator is presented. The proposed oscillator is the simplified version of the previous FLL oscillator with two separate resonators in the VCO and frequency detector. The resonator is commonly used in the VCO and frequency detector of the proposed oscillator configuration. The 5-GHz oscillator is implemented on the hetero-multilayer substrate composed of a Rogers' RO4350B laminate, which has excellent high-frequency performance, and the commercial FR4 three-layer substrate. The frequency locking occurs at approximately 5 GHz and has an output power of 3.8 dBm. The phase noise has a free-run VCO phase noise at frequencies above 1 kHz, and an FLL background noise at frequencies below 1 kHz. For this loop-filter, the phase noise showed an improvement of approximately 12 dB at the offset-frequency of 100 Hz.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.385-388
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• 2003

In this paper, a D-Latch is replaced by a memory cell on the proposed PFD to improve response tine by reducing reset me. The PFD has been simulated using HSPICE with a Hynix 0.35um CMOS process to prove the performance improvement.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.2A
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• pp.176-186
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• 2006

In this paper, we propose an enhanced symbol detector algorithm for 2.45GHz LR-WPAN(Low-Rate Wireless Personal Area Network) receiver. Because the frequency offset of $\pm$80ppm on 2.45GHz band is recommended in IEEE 802.15.4 LR-WPAN(Low-Rate Wireless Personal Area Network) specification, a symbol detector algorithm having stable operation in the channel environment with large frequency offset is required. For robustness to the frequency offset, non-coherent detection-based symbol detector algorithm is typically applied in the LR-WPAN receiver modem. However, the noncoherent symbol detector has increased performance degradation and hardware complexity due to squaring loss of I/Q squaring operation. Therefore we propose a coherent detection-based symbol detector algorithm with frequency offset compensation using a preamble symbol. The proposed algorithm is more suitable for LR-WPAN receiver aimed at low-cost, low-power and low-complexity than the non-coherent symbol detector, since it can reduce performance degradation due to squaring loss of I/Q squaring operation and implementation complexity. Simulation results show that the proposed algorithm has performance improvement of about 1dB in various channel environments.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.10A
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• pp.971-978
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• 2005

In this paper, we design and fabricate a VCO(Voltage Controlled Oscillator) for radar detector of X/K/Ka band using frequency multiplier. The existing VCO operated in radar detector have many Problems such as narrow bandwidth, slow frequency variable rate, unstable of production due to high frequency. So we design and fabricate a VCO improved such problems using frequency multiplier. As a result of measure, investigated frequency multiple VCO show its output power 3.64 dBm at multiplied operating frequency 11.27 GHz and have wide frequency tuning range of 660 MHz by controlled voltage 0V to 4.50 V applied diode. And also its phase noise is -104.0 dEc at 1 MHz offset frequency so we obtain suitable performance for commercial use.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.10
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• pp.76-81
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• 2013

A new phase frequency detector based digital phase-locked loop (PLL) of 125 MHz was designed using the 130 nm CMOS technology library consisting of inverting edge detectors along with a typical digital phase-locked loop to reduce the lock time and jitter for mid-frequency applications. XOR based inverting edge detectors were used to obtain a transition earlier than the reference signal to change the output more quickly. The HSPICE simulator was used in a Cadence environment for simulation. The performance of the digital phase-locked loops with the proposed phase frequency detector was compared with that of conventional phase frequency detector. The PLL with the proposed detector took $0.304{\mu}s$ to lock with a maximum jitter of approximately 0.1142 ns, whereas the conventional PLL took a minimum of $2.144{\mu}s$ to lock with a maximum jitter of approximately 0.1245 ns.

• ETRI Journal
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• v.35 no.2
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• pp.218-225
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• 2013

The pull-out frequency of a second-order phase lock loop (PLL) is an important parameter that quantifies the loop's ability to stay frequency locked under abrupt changes in the reference input frequency. In most cases, this must be determined numerically or approximated using asymptotic techniques, both of which require special knowledge, skills, and tools. An approximating formula is derived analytically for computing the pull-out frequency for a second-order Type II PLL that employs a sinusoidal characteristic phase detector. The pull-out frequency of such PLLs can be easily approximated to satisfactory accuracy with this formula using a modern scientific calculator.

• Journal of information and communication convergence engineering
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• v.8 no.3
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• pp.339-342
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• 2010

An iris image pattern positioning with preserved edge detector, ring zone and clock zone, frequency distribution and overlay matching is presented in this paper. Edge detector is required to be powerful and detail. That is proposed by overlaying Canny with LOG (CLOG). The two reference patterns are made from allocating each gray level on the clock zone and ring zone respectively. The normalized target image is overlaid with the clock zone reference pattern and the ring zone pattern to extract overlapped number, and make a matched frequency distribution to look through a symptom and position of human organ and tissue. The iterating experiments result in the ring and clock zone positioning evaluation.

• KIEE International Transactions on Electrophysics and Applications
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• v.4C no.6
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• pp.306-309
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• 2004

This paper presents a new active antenna consisting of a microstrip patch for the passive radiator, a mixer for frequency conversion, a voltage controlled oscillator (VCO) and a phase detector for phase control. The microwave signal frequency has been converted into intermediate frequency (IF) on the antenna elements by the mixer. The active antenna consists of two ports, the IF port has a transmitted IF signal via power combined to the baseband and the dc control port is under the control of the phase-detector. The input voltage of the VCO is controlled by the phase detector. The scan range of the array is determined by the phase detector and the VCO and is obtained between 30$^{\circ}$ and - 30$^{\circ}$

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.397-400
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• 2002

In this paper, a novel noncoherent multiuser detector with diversity reception for a differentially encoded DS/CDMA signal in a frequency-selective Rayleigh fading channel is proposed. The proposed receiver employs multipath decorrelator and decision feedback differential detector (DFDD) with diversity reception. DFDD performs differential encoding and diversity combining. The performance is obtained by analysis and simulation and it is sown that the proposed receiver outperforms conventional differential receiver with slight increase of complexity.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.963-966
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• 2003

This paper proposes a new locking algorithm of the delay locked loop (DLL) which reduces the lock-acquisition time and eliminates false locking problem to enlarge the operating frequency range. The proposed DLL uses the modified phase frequency detector (MPFD) and the modified charge pump (MCP) to avoid the false locking problem. Adopting a new lock detector that measures delay between elects helps the fast lock-acquisition time greatly. The idea has been confirmed by HSPICE simulations in a 0.35-${\mu}{\textrm}{m}$ CMOS process.