• 한국신재생에너지학회:학술대회논문집
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• 한국신재생에너지학회 2005년도 제17회 워크샵 및 추계학술대회
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• pp.665-665
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• 2005

The existing DSP for utility interactive photovoltaic generation system control generally uses floating point process type. Because it is easy to use for number crunching, however, it is too late and too expensive. Fixed point process DSP TMS320F2812, has high control speed and is rather inexpensive. A very complicated real system can be simulated using hardware-in-the-loop (HIL) system in a virtual environment Therefore, HIL system can speed up research and development process with a little effort. Also current DSP for utility interactive photovoltaic generation system adopts floating point process type, which is easy to use for number crunching. However, fixed point process DSF, TMS320F2812, has high control speed and is rather inexpensive. This paper presents more efficient method for MPPT control using TMS320F2812 along with HIL System.

• 한국통신학회논문지
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• 제21권2호
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• pp.365-374
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• 1996

Finite wordlength effects of the FS-1016 CELP(Code Excite Linear Prediction) vocoder algorithm) is analyzed, and a block floating-Point implementation method is employed to improve the fixed-point performance. An efficient run-time integer wordlength estimation algorithm is developed, and the overall system performance. An efficient run-time integer wordlength estimation algorithm is developed, and the overall system performance is verified in real-time using a TMS320C50 emulation board. Autoscaler software that conducts simulation-based automatic scaling to provide a floating-point like programming environment is used for this application development.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.873-874
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• 2006

In this paper, we have developed a ventricular fibrillation detection system based on DSP processor. The developed system was able to detect VF in real time correctly and quickly. We compared the performance of the floating point simulation with that of fixed point simulation. The computational cost of fixed point simulation was remarkably reduced than that of floating point simulation.

• 한국해양공학회:학술대회논문집
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• 한국해양공학회 2003년도 추계학술대회 논문집
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• pp.323-328
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• 2003

A basic design on a flexible riser in a floating type development system for upwelling deep ocean water is presented. In the numerical study, an implicit finite difference algorithm is employed for three-dimensional riser equations. Fluid and geometric non-linearity and bending stiffness are considered and solved by Newton-Raphson iteration. To keep the depth of end point of a flexible and light riser is very important for upwelling deep ocean water in a floating type development system. Weight attached at the end point of the riser in order to keep its intake depth is designed under the strong surface current and the configuration of the riser is predicted. The results of this study can be contributed to the design of the development system in floating type for upwelling deep ocean water.

• 한국물환경학회지
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• 제37권6호
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• pp.493-500
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• 2021

Floating solar photovoltaic (hereinafter PV) power generation is emerging as a proper alternative to overcome various environmental limitations of existing offshore PV generation. However, more government-led policy design and technical and institutional development are still required. Based on the policy agenda setting theory and technological innovation theory, this study contains the research questions concerning the co-evolution of technology and the floating solar PV policy. This study primarily evaluates the technological and institutional development level of floating solar PV policy through a survey of domestic floating solar PV experts. Secondly, we also analyze the kind of policy agenda that should be set a priori. Analyzing the priorities to be considered, the first environmental enhancement needs to be considered from both the technical and institutional aspects. The second candidate task for the policy agenda is residents' conflict and improvement of regulations. Both candidate tasks need to be actively considered in the policy agenda from the institutional point of view. The third is publicity, profit sharing, follow-up monitoring, and cost. Among them, public relations and profit sharing are tasks that need to be considered in the policy agenda from the institutional point of view. On the other hand, the cost of follow-up monitoring should be considered as a policy agenda in terms of technology, system, and common aspects. Finally, there are technical standards. Likewise, technical standards need to be considered in the policy agenda in terms of both technical and institutional commonality.

• 문화기술의 융합
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• 제9권4호
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• pp.625-631
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• 2023

본 연구는 레일플로팅궤도의 실제거동을 반영할 수 있는 해석모델을 제안하는 연구로써 현장측정과 수치해석을 통해 가장 합리적인 모델을 분석 하였다. 레일플로팅궤도의 현 설계이론 해석결과는 현장측정 결과와 상이하게 나타나서 실제거동을 반영하기에 적합하지 않은 것으로 분석 되었다. 레일플로팅궤도는 레일의 휨에 의한 변위 보다는 지점의 침하가 전체 변위량에 직접적인 영향을 미치는 것으로 분석 되었다. 수치해석 결과 레일직하부에 지지점을 갖지 않는 병렬배치 스프링모델인 제안모델의 해석결과가 실제거동을 반영하는 것으로 분석 되었다. 본 연구에서 제시된 해석모델은 향후 레일플로팅궤도에 대한 설계 및 유지관리시 궤도거동 예측에 활용이 가능하다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2005년도 추계종합학술대회
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• pp.711-714
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• 2005

We propose floating point arithmetic units for geometry operation of mobile 3D graphic processor. The proposed arithmetic units conform to the single precision format of IEEE standard 754-1985 that is a standard of floating point arithmetic. The rounding algorithm applies the nearest toward zero form. The proposed adder/subtraction unit and multiplier have one clock cycle latency, and the inversion unit has three clock cycle latency. We estimate the required numbers of arithmetic operation for Viewing transformation. The first stage of geometry operation is composed with translation, rotation and scaling operation. The translation operation requires three addition and the rotation operation needs three addition and six multiplication. The scaling operation requires three multiplication. The viewing transformation is performed in 15 clock cycles. If the adder and the multiplier have their own in/out ports, the viewing transformation can be done in 9 clock cycles. The error margin of proposed arithmetic units is smaller than $10^{-5}$ that is the request in the OpenGL standard. The proposed arithmetic units carry out operations in 100MHz clock frequency.

• 제어로봇시스템학회논문지
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• 제22권7호
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• pp.513-518
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• 2016

The piezoelectric actuating device is known for its large power density and simple structure. It can generate a larger force than a conventional actuator and has also wide bandwidth with fast response in a compact size. To control the piezoelectric actuator, we need an analog signal conditioning circuit as well as digital microcontrollers. Conventional microcontrollers are not equipped with an analog part and need digital-to-analog converters, which makes the system bulky compared with the small size of piezoelectric devices. To overcome these weaknesses, we are developing a single-chip controller that can handle analog and digital signals simultaneously using mixed-signal FPGA technology. This gives more flexibility than traditional fixed-function microcontrollers, and the control speed can be increased greatly due to the parallel processing characteristics of the FPGA. In this paper, we developed a floating-point multiplier, PWM generator, 80-kHz power control loop, and 1-kHz position feedback control loop using a single mixed-signal FPGA. It takes only 50 ns for single floating-point multiplication. The PWM generator gives two outputs to control the charging and discharging of the high-voltage output capacitor. Through experimentation and simulation, it is demonstrated that the designed control loops work properly in a real environment.

• 방송공학회논문지
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• 제13권3호
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• pp.415-418
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• 2008

소형의 휴대용 단말기는 회로복잡도나 소비전력 등의 문제로 부동소수점 연산 프로세서를 탑재하지 않는 경우가 있는데, 이로 인해 오디오 데이터의 디코딩 시간이 길어져, 끊김이나 잡음이 발생한다. 본 논문에서는 이를 해결하기 위해서 MPEG-4 오디오 디코딩 시 수행되는 실수형 연산과정을 정수형 연산과정으로의 변환을 통하여 디코딩 속도를 향상 시킬 수 있는 알고리즘을 제안하고 실험결과를 통해서 효율성을 보인다.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2010년도 춘계학술대회
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• pp.320-323
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• 2010

본 논문은 작은 사이즈가 요구되는 제한적인 모바일 환경의 프로세서에서 별도의 연산기 없이 제안된 Dual Phase 명령어 구조를 이용해 효율적인 로그와 지수 연산이 가능한 방법을 제안한다. Floating Point 자료형의 지수부와 실수부를 추출하는 명령어 세트와 테일러 급수 전개를 이용해 로그의 근사치를 계산하여 24비트 단정도 부동 소수점을 연산하고, Dual Phase 명령어 구조를 활용해 명령어 실행 사이클을 줄였다. 제안된 구조는 별도의 연산기를 두는 구조보다 작은 사이즈를 유지하면서 성능저하를 33%까지 최소화 할 수 있는 구조이다.