• Journal of the Microelectronics and Packaging Society
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• v.24 no.2
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• pp.11-15
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• 2017

As the heat dissipation problem is increased in 3D multi flip chip packages, an improvement of thermal conductivity in bonding interfaces is required. In this study, the effect of alumina filler addition was investigated in non-conductive paste(NCP). The fine alumina filler having average particles size of 400 nm for the fine pitch interconnection was used. As the alumina filler content was increased from 0 to 60 wt%, the thermal conductivity of the cured product was increased up to 0.654 W/mK at 60 wt%. It was higher value than 0.501 W/mK which was reported for the same amount of silica. It was also found out that the addition of fine sized alumina filler resulted in the smaller decrease in thermal conductivity than the larger sized particles. The viscosity of NCP with alumina addition was increased sharply at the level of 40 wt%. It was due to the increase of the interaction between the filler particles according to the finer particle size. In order to achieve the appropriate viscosity and excellent thermal conductivity with fine alumina fillers, the highly efficient dispersion process was considered to be important.

• Journal of the Microelectronics and Packaging Society
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• v.17 no.3
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• pp.1-9
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• 2010

We reported the methodology for the shear test which is one of the evaluation procedure for mechanical reliability of flip-chip package. The shear speed and the tip height are found to be two significant experimental parameters in the shear test. We investigated how these two parameters have an influence on the results, the shear strength and failure mode. In order to prove these experimental inconsistency, simulation using finite element analysis was also conducted to calculate the shear strength and to figure out the distribution of plastic energy inside of the solder ball. The shear strength decreased while the tip height increased or the shear speed decreased. A variation in shear strength due to inconsistent shear conditions made confusion on analyzing experimental results. As a result, it was strongly needed to standardize the shear test method.

• Journal of the Microelectronics and Packaging Society
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• v.30 no.3
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• pp.1-10
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• 2023

Recently, as the demand for high-performance computers and mobile products increases, semiconductor packages are becoming high-integration and high-density. Therefore, in order to transmit a large amount of data at once, micro bumps such as flip-chip and Cu pillar that can reduce bump size and pitch and increase I/O density are used. However, when the size of the bumps is smaller than 70 ㎛, the brittleness increases and electrical properties decrease due to the rapid increase of the IMC volume fraction in the solder joint, which deteriorates the reliability of the solder joint. Therefore, in order to improve these issues, a layer that serves to prevent diffusion is inserted between the UBM (Under Bump Metallization) or pillar and the solder cap. In this review paper, various studies to improve bonding properties by suppressing excessive IMC growth of micro-bumps through additional layer insertion were compared and analyzed.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.32 no.2
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• pp.186-193
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• 2008

[ $Moir{\acute{e}}$ ] interferometry is an optical method, providing whole field contour maps of in-plane displacements with high resolution. The demand for enhanced sensitivity in displacement measurements leads to the technique of microscopic $moir{\acute{e}}$ interferometry. The method is an extension of the $moir{\acute{e}}$ interferometry, and employs an optical microscope for the required spatial resolution. In this paper, the sensitivity of $moir{\acute{e}}$ interferometry is enhanced by an order of magnitude using an immersion interferometry and the optical/digital fringe multiplication(O/DFM) method. In fringe patterns, the contour interval represents the displacement of 52 nm per fringe order. In order to estimate the reliability and the applicability of the optical system implemented, the measurements of rigid body displacements of grating mold and the coefficient of thermal expansion(CTE) for an aluminium block are performed. The system developed is applied to the measurement of thermal deformation in a flip chip plastic ball grid array package.

• Proceedings of the KIEE Conference
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• 2005.11a
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• pp.30-32
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• 2005

This paper reports on an LTCC-based packaging method using Au/Sn eutectic bonding process for RF MEMS applications. The proposed packaging structure was realized by a micromachining technology. An LTCC substrate consists of metal filled vertical via feedthroughs for electrical interconnection and Au/Sn sealing rim for eutectic bonding. The LTCC capping substrate and the glass bottom substrate were aligned and bonded together by a flip-chip bonding technology. From now on, shear strength and He leak rate will be measured then the fabricated package will be compared with the LTCC package using BCB adhesive bonding method which has been researched in our previous work.

• Journal of the Korean Institute of Intelligent Systems
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• v.22 no.6
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• pp.694-699
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• 2012

In this paper, semiconductor package inspection results using white light interferometer with large F.O.V., in order to apply semiconductor product inspection process, are shown. Experimental 3D data repeatability test results for the same special bumps of each substrate are shown. Experimental 3D data repeatability test results for all the bumps in each substrate are also shown. Semiconductor package inspection using white light interferometer with large F.O.V. is very important for the fast 3D data inspection in semiconductor product inspection process. This paper is surely helpful for the development of in-line type fast 3D data inspection machine.

• Journal of the Microelectronics and Packaging Society
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• v.9 no.3
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• pp.31-36
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• 2002

The 2nd level solder joint reliability of 153 FC-BGA for high-speed SRAM (Static Random Access Memory) with the large chip on laminate substrate comparing to PBGA(Plastic Ball Grid Array) was studied in this paper. This work has been done to understand an influence as the mounting with single side or double sides, structure of package, properties of underfill, properties and thickness of substrate and size of solder ball on the thermal cycling test. It was confirmed that thickness of BT(bismaleimide tiazine) substrate increased from 0.95 mm to 1.20 mm and solder joint fatigue life improved about 30% in the underfill with the low young's modulus. And resistance against the solder ball crack became twice with an increase of the solder ball size from 0.76 mm to 0.89 mm in solder joints.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.8
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• pp.625-631
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• 2009

In this thesis, lateral thermosonic bonding with ACFs was investigated as a process to make high reliability joints for FPD fabrication. Conditions for thermosonic and thermocompression bonding with ACFs were determined and used to make specimens in a driving test jig for testing of bond reliability by thermal shock. The results showed that thermosonic bonding temperature of $199\;^{\circ}C$ and bonding time of 1s produced bonds with good reliability. Additionally, thermosonic bonding temperature and time were reduced and thermal shock test results compared to this proposed curing condition. It is concluded that theromosonic bonding with ACFs can be effectively applied to reduce bonding temperature and time compared with that of thermocompression bonding.

• Journal of Welding and Joining
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• v.32 no.3
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• pp.53-59
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• 2014

The mechanical stability of solder joints in electronic devices with Sn-Ag-Cu is a continuous issue since the material was applied to the industry. Various shock test methods were developed and standardized tests are used in the industry worldwide. Although it is applied for several years, the detailed mechanism of the shock induced failure mechanism is still under investigation. In this study, the effect of external temperature was observed on large Flip-chip BGA components. The weight and size of the large package produced a high strain region near the corner of the component and thus show full fracture at around 200G level shock input. The shock performance at elevated temperature, at $100^{\circ}C$ showed degradation based on board pad designs. The failure mode and potential failure mechanisms are discussed.

• Proceedings of the KWS Conference
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• 2007.11a
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• pp.150-152
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• 2007

It has been known that the underfilling technique is effective in reducing thermal and environmental stress concentration at solder joint in FC asscemblies. In this paper, the effect of thermomechanical properties of underfill such as coefficient of thermal expansion(CTE) and Young's modulus on reliability of FC assembly under thermal cycling was investigated. For parametric study for optimal design of underfill, finite element analyses(FEA) were performed for seven different CTEs and five different Young's modulus. The results show that the concentrated maximum stress decreases as Young's modulus of underfill increases and the CTE of underfill decreases.